Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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01 Jan 2005
TL;DR: Rahman and Anisur as discussed by the authors proposed a general theoretical approach for the quantum mechanical simulation of n-MOSFETs within the Non Equilibrium Green's Function (NEGF) formalism, and its application is demonstrated by performing a scaling study for the end of the ITRS Ge device.
Abstract: Rahman, Anisur. Ph.D., Purdue University, December, 2005. Exploring New Channel Materials for Nanoscale CMOS Devices: A Simulation Approach. Major Professor: Mark Lundstrom and Gerhard Klimeck. The improved transport properties of new channel materials, such as Ge and III-V semiconductors, along with new device designs, such as dual gate, tri gate or FinFETs, are expected to enhance the performance of nanoscale CMOS devices. Novel process techniques, such as ALD, high-κ dielectrics, and metal gates are now being used to experimentally explore such devices. New materials in the channel promise reduced series resistance and higher on-currents. The theoretical assessment of such devices is a challenge because bandstructure, arbitrary wafer orientation, quantum effects and electrostatics must all be treated. In the first part of this work, a general theoretical approach for the quantum mechanical simulation of n-MOSFETs within the Non Equilibrium Green’s Function (NEGF) formalism is introduced, and its application is demonstrated by performing a scaling study for the end of the ITRS Ge device. In the second part of this work, a systematic analysis of the bandstructure effects in deeply scaled nand pMOSFETs with Si, Ge, GaAs and InAs channel is performed. Here, a 20 orbital sp3d5s∗-SO tight-binding model and a top-of-thebarrier quasi-2D ballistic transport model have revealed important trends in deeply scaled new channel material devices.
11 citations
Patent•
09 May 2003
TL;DR: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate, and a plurality of semiconductor islands overlie the buried layer as discussed by the authors.
Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.
11 citations
01 Sep 2006
TL;DR: In this article, the effect of different scattering mechanisms and of the subband structure is analyzed in detail for n-MOSFETs featuring bulk and double-gate architecture with 25nm gate length.
Abstract: In this paper, the authors use multi-subband-Monte-Carlo simulations to investigate the on-current increment induced by biaxial strain in n-MOSFETs featuring bulk and double-gate architecture with 25nm gate length. The effect of different scattering mechanisms and of the subband structure is analyzed in detail
11 citations
Cites background or methods from "Fabrication and analysis of deep su..."
...We have thus decided to maintain the calibration on Takagi’s curve for the unstrained case, and then to verify if it reproduces the relative mobility enhancement measured in [2], [3] (i....
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...Many authors have reported substantial electron mobility enhancement in biaxially strained silicon channels grown on relaxed SiGe substrates [2], [3]....
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...1 shows that the mobility of the unstrained devices in [2], [3] do not lay on well known universal curve [16], that we used to calibrate our MSMC in conventional Si [13] (circles in Fig....
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Patent•
TSMC1
TL;DR: In this article, a tensilely strained semiconductor is formed from silicon having a thickness less than its critical thickness, and the tensile-strained semiconductor can be formed from any silicon having germanium concentration at least 10 atomic %.
Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.
10 citations
01 Jan 2007
TL;DR: In this paper, a review of the strained-Si CMOS technology with an emphasis on the mechanism of mobility enhancement due to strain is presented. And experimental results on implementing strain into CMOS channels are described.
Abstract: Improvement in performance of Si MOSFETs through conventional device scaling has become more difficult, because of several physical limitations associated with the device miniaturization. Thus, much attention has recently been paid to the mobility enhancement technology through applying strain into CMOS channels. This chapter reviews this strained-Si CMOS technology with an emphasis on the mechanism of mobility enhancement due to strain. The device physics for improving drive current of MOSFETs is summarized from the viewpoint of electronic states of carriers in inversion layers and, in particular, the subband structures. In addition, recent experimental results on implementing strain into CMOS channels are described.
10 citations
References
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IBM1
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations