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Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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Citations
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Journal ArticleDOI
TL;DR: In this article, the authors investigated the physics behind the overall on-current (Ion) improvement of n-channel metal-oxide-semiconductor (NMOS) transistors by uniaxial tensile stress.
Abstract: This paper investigates the physics behind the overall on-current (Ion) improvement of n-channel metal-oxide-semiconductor (NMOS) transistors by uniaxial tensile stress. The strain-induced change in subthreshold off-current (Ioff) is related to the following strain-induced effects: (i) mobility enhancement, (ii) reduction in the saturation threshold voltage (Vth,sat), and (iii) improvement in subthreshold swing (Sts). By selecting transistors whose Ioff is less sensitive to the statistical variation in gate length, we studied the effects of process-induced tensile stress on Ion and Ioff of NMOS transistors. We found that both externally applied tensile stress and process-induced tensile stress led to a bigger percentage increase in subthreshold Ioff compared to the percentage increase in Ion. Our explanation is that the increase in Ioff is mainly due to an increase in mobility and a decrease in Vth,sat by tensile stress. The improvement of subthreshold swing by tensile stress can lead to a decrease in sub...

8 citations

Proceedings ArticleDOI
25 Apr 2004
TL;DR: In this paper, the authors investigated off-state current leakage in strained silicon NMOSFETs built on supercritical thickness strained silicon films and proposed a simple conceptual model for the offstate leakage: the leakage is caused by enhanced dopant diffusion near misfit dislocations.
Abstract: This paper investigates off-state current leakage in strained silicon NMOSFETs built on supercritical thickness strained silicon films. it describes a simple conceptual model for the off-state leakage: the leakage is caused by enhanced dopant diffusion near misfit dislocations. This paper studies the validity of this hypothesis using both DC IV measurements and photon emission microscopy measurements of NMOSFETs with several different supercritical strained silicon thickness values. It shows that the emission measurements of the off-state leakage and the gate length dependence of the off-state leakage can both be easily explained by the leakage model. It also demonstrates that the response to an applied gate or back-bias voltage of the IV characteristics and the light emission data can be understood within the context of the proposed conceptual model.

8 citations

Journal ArticleDOI
TL;DR: A simulator has been developed for evaluating the voltage transfer characteristics (VTC) and analyzing some performance parameters of such devices-based CMOS inverters and can be applied to any novel device structure and complex digital logics.

8 citations


Cites background from "Fabrication and analysis of deep su..."

  • ...1b shows the schematic representation of a S–Si MOSFET under various bias conditions along with S/D series resistance (RS and RD) as it is equally important for strained devices [3,20,27]....

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  • ...kn(p)1⁄4 2an(p)vsat,n(p)τw,n(p)/3, is a parameter which depends on strain [3], relaxation time of carriers (τw,n(p)) [32,33] and an(p) which is a fitting parameter which depends on the technological features of the device [32]....

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Journal ArticleDOI
TL;DR: In this paper, the formation of Ni silicides on Si 1-y C y (0 ≤ y ≤ 0.02) epilayers grown on Si(001) was investigated and an abnormal redistribution of C atoms in the NiSi thin films was observed during Ni silicidation.
Abstract: This study investigates the formation of Ni silicides on Si 1-y C y (0 ≤ y ≤ 0.02) epilayers grown on Si(001). The presence of C atoms retards the growth kinetics of NiSi and significantly enhances the thermal stability of NiSi thin films. In particular, an abnormal redistribution of C atoms in the NiSi thin films was observed during Ni silicidation. The NiSi layer was split into two sublayers by an obvious pileup of C atoms. This study proposes a mechanism to elucidate this phenomenon in terms of the C solubility. C atoms accumulated at the NiSi/S 1-y C y interfaces and NiSi grain boundaries may act as diffusion barriers, effectively hindering the grain growth and agglomeration of NiSi and extending the process window of low resistivity NiSi silicides.

8 citations

Journal ArticleDOI
TL;DR: In this article, a detailed study of quasi-ballistic transport in submicron semiconductor channels is presented, where the electron distribution in such channels differs significantly from a near-equilibrium, shifted Maxwell-Boltzmann distribution function, and displays a large broadening, as well as pronounced features, peaks and shoulders, in the high-velocity tail of the distribution associated with the nonequilibrium and quasiballistic nature of the electron transport.
Abstract: We present a detailed study of quasi-ballistic transport in submicron semiconductor channels. The electron distribution in such channels differs significantly from a near-equilibrium, shifted Maxwell-Boltzmann distribution function, and displays a large broadening, as well as pronounced features, peaks and shoulders, in the high-velocity tail of the distribution associated with the nonequilibrium and quasi-ballistic nature of the electron transport. For submicron channel lengths, analyses of the spatial dependence of the velocity distribution function show that scattering in the entire channel is important and that the scattering efficiency has a strong spatial dependence. In this article, we particularly study the crossover between the diffusive and quasi-ballistic regimes of transport and find characteristic signatures in (i) the electrostatics, which manifests as a redistribution of the voltage drop from the channel to the contact regions; (ii) the electron density, where exponential and linear spatial dependences of the source-injected and channel- and drain-backscattered electron densities are signatures of diffusive and quasi-ballistic transport, respectively, and (iii) the electron distribution function, where the source-injected ballistic peak observed in the quasi-ballistic regime disappears at the onset of diffusive transport.

8 citations

References
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Journal ArticleDOI
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...

1,500 citations

Journal ArticleDOI
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

1,389 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.

556 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

454 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

358 citations