Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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TL;DR: In this article, the performance of ground plane and strained silicon on FDSOI MOSFETs is investigated and the 2D ATLAS simulations are done and the simulation model is validated with previously published experimental results.
Abstract: In the present work, we have investigated the performance of ground plane and strained silicon on FDSOI MOSFETs. The 2D ATLAS simulations are done and the simulation model is validated with previously published experimental results. The transfer characteristics, DIBL, Vt, Ion and Ioff of all the structures are analyzed for 25 nm and 32 nm gate length. The effect of body thickness on device performance is also evaluated. Strained device offer higher drive current, but increases the leakage current. We have applied the ground plane to reduce the leakage current. The DIBL is higher for the strained device. DIBL in GPS and GPB structures (strained and unstrained) is almost same, and is lower than conventional FDSOI structure. The FDSOI devices have the lowest threshold voltage as compared to the GP and GPB devices, with GPB offering the highest Vt. The drain current is observed to increases almost linearly with body thickness. The deployment of ground plane and strained silicon on FDSOI MOSFET shows promise to substitute conventional MOSFET for high speed and low power applications.
7 citations
Cites background from "Fabrication and analysis of deep su..."
...The most effective way to introduce high tensile strain to the channel is to epitaxial grow strained silicon on a relaxed silicon germanium (Si-Ge) layer [6]....
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TL;DR: In this paper, an ensemble self-consistent Monte Carlo simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings is presented.
Abstract: Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin–orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of ...
7 citations
01 Jan 2013
TL;DR: In this article, the authors derived a spin-dependent Hamiltonian that captures the symmetry of the zone edge X-point states in direct-absorption edge transitions, and presented an analytical expression of the spindependent states and of spin relaxation due to electron-phonon interactions.
Abstract: Group IV semiconductors are natural material
choices for spintronic devices. Space-inversion symmetry precludes
spin relaxation by the Dyakonov-Perel mechanism. Hyperfine
interactions are suppressed due to the natural abundance of
zero-spin nuclear isotopes. As a result, the intrinsic spin
lifetime is relatively long (~10 ns at room temperature in
nondegenerate n-type silicon). Combined with the dominant role of
Si and Ge in the semiconductor industry, there is a wide interest
in recent experiments with Si and Ge
spintronics. The conservation of angular
momentum during the radiation-matter interaction allows one to
study the spin of charge carriers from the state of light
polarization. Si was the first material studied in optical
orientation experiment. However, a parameter-free method of
determining the spin polarization of electrons in Si and Ge was
missing for decades. This missing link is established in this
dissertation with a comprehensive theory, which provides concise
selection rules of spin-dependent optical transitions. These
indirect absorption edge transitions involve the interaction with
phonons, whose symmetries are crucial in elucidating recent spin
injection experiments in Si and Ge. The theory also studies the
effect of strain. Strain lifts the band edges degeneracies and
controls the mixing
between holes with different angular momenta,
and could be used to regulate and validate the relation between
measured circular polarization degrees and electron spin
polarizations. The availability of
transparent spin-dependent theories in direct gap semiconductors
has spurred the field of spintronics. Prior to our work, however,
the study of spin-orbit properties in indirect bandgap Si requires
elaborate numerical methods. To establish a lucid and compact
theory, we derive a spin-dependent Hamiltonian that captures the
symmetry of the zone edge X-point states in Si. We present
analytical expressions of the spin-dependent states and of spin
relaxation due to electron-phonon interactions, showing excellent
agreement with experimental results. In addition, we investigate
the intrinsic spin relaxation of conduction electrons in Ge.
Spin-flip matrix elements are derived for a general spin
orientation that quanties the anisotropy of spin relaxation. Spin
lifetimes from integrations of these matrix elements show excellent
agreement with independent elaborate numerical
calculation.
7 citations
TL;DR: In this article, a surface bulging effect in the electron Δ4 wavefunction was found to increase surface roughness scattering for these states, and the origin of this effect can be explained by moving beyond the effective mass approximation and contrasting the properties of the Δ2 and Δ4 Wavefunctions in a representation that comprehends full crystal and Bloch state symmetry.
Abstract: A seemingly anomalous enhancement of electron mobility in strained silicon inversion layers has exposed a gap between device physics theory and experiment in recent years. At the root of this discrepancy is a surface bulging effect in the electron Δ4 wavefunction, which increases surface roughness scattering for these states. Complementary metal oxide semiconductor strain engineering reduces Δ4 state occupancy, thereby reducing surface roughness scattering in the channel. The origin of this effect can be explained by moving beyond the effective mass approximation and contrasting the properties of the Δ2 and Δ4 wavefunctions in a representation that comprehends full crystal and Bloch state symmetry.
6 citations
22 Mar 2004
TL;DR: In this paper, a review of the development of strained-Si CMOS with emphasis on the electrical properties is presented, including the device parameters extracted from the physical models, indispensable in describing the electrical characteristics.
Abstract: Recent progress on the development of strained-Si CMOS is reviewed with emphasis on the electrical properties. The device parameters extracted from strained-Si CMOS and the physical models, indispensable in describing the electrical characteristics, are presented. In addition, new requirements for device characterization, specific to strained-Si devices, which include V/sub th/ control and influence of Ge, are also addressed.
6 citations
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TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations