Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
Citations
More filters
01 Jan 2011
4 citations
Cites background from "Fabrication and analysis of deep su..."
...Based on the lattice mismatch between Si and SiGe, the biaxial stress is exerted by depositing a pseudomorphic Si layer on a relaxed SiGe substrate [8]....
[...]
TL;DR: In this paper, the authors show that a higher value of the dielectric constant in SiGe relative to that in Si causes a reduction in the magnitude of the threshold voltage in strained-Si/SiGe n- and p-MOSFETs.
Abstract: We show that a higher value of the dielectric constant in SiGe relative to that in Si causes a reduction in the magnitude of the threshold voltage in strained-Si/SiGe n- and p-MOSFETs. This reduction increases with decreasing thickness of the strained-Si layer. Our results are consistent with the observed mismatch between calculated and measured threshold voltage shifts in strained-Si MOSFETs.
4 citations
TL;DR: In this article, the authors show that the anomalous enhancement of electron mobility in strained silicon inversion layers at high sheet densities is due to a bulging effect in the electron \Delta 4 wavefunction at the silicon surface.
Abstract: A seemingly anomalous enhancement of electron mobility in strained silicon inversion layers at high sheet densities has exposed a conspicuous gap between device physics theory and experiment in recent years. We show that the root of this discrepancy is due to a bulging effect in the electron \Delta 4 wavefunction at the silicon surface. This renders \Delta 4 electrons more susceptible to perturbations in surface structure thereby increasing surface roughness scattering for these states. Strain engineering utilized by the CMOS industry reduces the relative occupancy of the \Delta 4 states resulting in less overall surface roughness scattering in the channel. We show that the origin of this effect can be explained by moving beyond the effective mass approximation and contrasting the properties of the \Delta 2 and \Delta 4 wavefunctions in a representation that comprehends full crystal and Bloch state symmetry.
4 citations
TL;DR: In this article, a gate length/width of 80 nm/0.6 /spl mu/m for bulk nMOSFETs without degrading the device performance was achieved with 1.7nm gate oxide, 80-nm gate length, and 1.2V operation voltage.
Abstract: Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6 /spl mu/m for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917 /spl mu/A//spl mu/m for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.
4 citations
TL;DR: Combined wet and dry cleaning via hydrofluoric acid (HF) and atomic hydrogen on Si0.6Ge0.4(001) surface was studied at the atomic level using ultrahigh vacuum scanning tunneling microscopy (STM) and x-ray photoelectron spectroscopy to understand the chemical transformations of the surface as discussed by the authors.
Abstract: Combined wet and dry cleaning via hydrofluoric acid (HF) and atomic hydrogen on Si0.6Ge0.4(001) surface was studied at the atomic level using ultrahigh vacuum scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and x-ray photoelectron spectroscopy to understand the chemical transformations of the surface. Aqueous HF removes native oxide, but residual carbon and oxygen are still observed on Si0.6Ge0.4(001) due to hydrocarbon contamination from post HF exposure to ambient. The oxygen contamination can be eliminated by shielding the sample from ambient via covering the sample in the HF cleaning solution until the sample is introduced to the vacuum chamber or by transferring the sample in an inert environment; however, both processes still leave carbon contaminant. Dry in-situ atomic hydrogen cleaning above 330 °C removes the carbon contamination on the surface consistent with a thermally activated atomic hydrogen reaction with surface hydrocarbon. A postdeposition anneal at 550 °C ind...
4 citations
References
More filters
IBM1
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations