Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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Patent•
25 Jun 2003TL;DR: A SiGe monocrystalline etch-stop material system is used for micromachining by aqueous anisotropic etchants of silicon such as TMAH and hydrazine as discussed by the authors, which can vary in exact composition but is a doped or undoped Si 1−x Ge x alloy with x generally between 0.2 and 0.5.
Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si 1−x Ge x alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×10 19 cm −3 of boron or undoped Si 1−x Ge x alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si 1−x Ge x alloy should not affect the etch-stop behavior. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material. Nominally, the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/buffer interface to a composition of germanium, and dopant if also present, at the buffer/etch-stop interface which can still be etched at an appreciable rate. Here, there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant. This process and layer structure allows for an entire range of new materials for microelectronics. The etch-stop capabilities introduce new novel processes and structures such as relaxed SiGe alloys on Si, SiO 2 , and SiO 2 /Si. Such materials are useful for future strained Si MOSFET devices and circuits.
129 citations
Patent•
TSMC1
TL;DR: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate as mentioned in this paper, and a first silicon island with a surface of a first crystal orientation overlies the insulator, and a second silicon island having a surface on the other side of the substrate also overlies it.
Abstract: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.
128 citations
Patent•
14 Jun 2002
TL;DR: In this paper, a method for forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate is described, which includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer with a second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layers to expose said second layer.
Abstract: A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.
128 citations
TL;DR: In this paper, the authors investigate how effective electron mobility at low lateral electric fields relates to velocity in the MOSFET saturation regime, where lateral fields in the channel are high.
Abstract: The importance of low-field mobility to the performance of deep-sub-100-nm bulk MOSFETs is not well understood. In this work, we investigate experimentally how effective electron mobility at low lateral electric fields relates to velocity in the MOSFET saturation regime, where lateral fields in the channel are high. For short (L/sub eff//spl ap/45 nm) NMOS devices, mobility is modified by externally applying uniaxial stress and the corresponding shifts in electron velocity are found to be significant.
127 citations
Cites background from "Fabrication and analysis of deep su..."
...Experimental demonstrations of strained silicon technology [5], [6] suggest that low-field mobility is important to sub100-nm bulk MOSFET performance....
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Patent•
14 Mar 2003
TL;DR: In this paper, the authors describe methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer.
Abstract: Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
126 citations
References
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IBM1
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations