Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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01 Jan 2015
TL;DR: In this article, the authors discuss random and systematic mismatch in passive and active components, mismatch characterization, and process and design methods to reduce mismatch, focusing on low-frequency noise.
Abstract: Component mismatch limits the precision of analog circuits, such as converters and current mirrors, and noise ultimately sets a lower limit on signals that can be detected and processed. Both mismatch and noise can have a large impact on the precision of analog and mixed-signal circuits. The first part of this chapter discusses random and systematic mismatch in passive and active components, mismatch characterization, and process and design methods to reduce mismatch. The second part describes the different noise mechanisms, focusing on low-frequency noise and methods to reduce it.
3 citations
TL;DR: In this paper, an intermediate Si layer in Si1?xGex film, replacing the conventionally compositional graded buffer layer, was used to fabricate a relaxed SiGe substrate of high quality.
Abstract: An intermediate Si layer in Si1?xGex film, replacing the conventionally compositional graded buffer layer, was used to fabricate a relaxed SiGe substrate of high quality. The intermediate Si layer changes the relaxation mechanism of the SiGe thin film via the generation of {3?1?1} dislocation loops. The {3?1?1} dislocation loops are formed in the intermediate Si layer to prompt a state of relaxation in the SiGe overlayer, provide the defects for trapping of threading dislocations (TDs) and leave a SiGe top layer with low dislocation density. For the SiGe/Si/SiGe samples, the residual strain and TDs on the top SiGe layer are independent of the SiGe underlayer thickness. With a 700 nm thick Si0.8Ge0.2 overlayer, such a Si0.8Ge0.2/Si/Si0.8Ge0.2 heterostructure with a smooth surface has a TD density of 8.9 ? 105 cm?2 and 3% residual strain. Owing to the different main relaxation mechanisms in SiGe films, the surface root mean square roughness of this relaxed buffer with a low density of surface pits was measured to be about 3 nm, which is lower than that of the sample without any intermediate Si layer (13 nm). Relaxation of the SiGe overlayer depends on the thickness of the intermediate Si layer. Optimization on relaxation in the SiGe/Si/SiGe structure with an intermediate Si layer of 50 nm is done. Strained Si n-channel metal-oxide-semiconductor field effect transistors with various buffer layers were fabricated and examined. The effective electron mobility for the strained Si device with this novel substrate technology was found to be 80% higher than that of the Si control device. The SiGe thin films with the intermediate Si layer serve as good candidates for high-speed strained Si devices. The global strain in the Si channel with a SiGe/Si/SiGe buffer is still beneficial for short channel devices.
3 citations
13 Nov 2009
TL;DR: In this article, the authors review several cases where parameter-free, atomic-scale, quantum mechanical calculations led to the identification of specific physical mechanisms for phenomena relating to performance, reliability, radiation effects, and aging issues in microelectronics.
Abstract: The development of engineering-level models requires adoption of physical mechanisms that underlie observed phenomena. This paper reviews several cases where parameter-free, atomic-scale, quantum mechanical calculations led to the identification of specific physical mechanisms for phenomena relating to performance, reliability, radiation effects, and aging issues in microelectronics. More specifically, we review recent calculations of electron mobilities that are based on atomic-scale models of the Si-Si O2 interface and elucidate the origin of strain-induced mobility enhancement. We then review extensive work that highlights the role of hydrogen as the primary agent of reliability phenomena such as Negative Bias Temperature Instability (NBTI) and radiation effects, such as Enhanced Low Dose Radiation Sensitivity (ELDRS) and dopant deactivation. Finally, we review atomic-scale simulations of recoils induced by energetic ions in Si and Si O2 . The latter provide a natural explanation for single-event gate rupture (SEGR) in terms of defects with energy levels in the Si O2 band gap.
2 citations
TL;DR: In this paper, a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations is presented.
Abstract: We report a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations. The study shows the remarkable role of the SiO2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si1–xGex. We found very specific annealing conditions to relax SGOI while keeping a homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO2 at this temperature, which would allow layer-by-layer matter redistribution. Remarkably, the Si layer epitaxially grown on relaxed SGOI remains fully strained with −0.85% tensile strain. The absence of strain sharing (between Si1–xGex and Si) is explained by the rigidity of the Si1–xGex/BOX interface at low temperature. Elastic simulations of the real system show that, because of the very specific elastic characteristics of SiO2, there are unique experimental conditions that both relax Si1–xGex and keep Si strained. Various epitaxial processes could be revisited in light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switch applications and for many other applications.
2 citations
TL;DR: This chapter presents a review of some of the recent results in the semiconductor industry, including the continued shrinking of its feature sizes, and the need of a more accurate forecast defined the International Technology Roadmap for Semiconductors (ITRS).
Abstract: Since the invention of the integrated circuit (IC) in 1958, engineers and researchers around the world have worked on how to put more speed, performance and value onto smaller chips of silicon. The semiconductor industry has made considerable progress, especially regarding the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The fundamental driver has been the continued shrinking of its feature sizes, allowing the exponential growth in device count that tracks the well-known Moore's Law, first formulated by Intel co-founder Gordon Moore. However, this law is a rough prediction of the future of IC expansion. The need of a more accurate forecast defined the International Technology Roadmap for Semiconductors (ITRS), which has been predicting and driving the pace of semiconductor technology at the same time.
The use of CMOS technology also for high-frequency (HF) applications is now common. This is due to the significant increase in the unity current gain frequency of modern deep submicrometer MOS devices. However, to be competitive against other technologies for high-frequency (HF) applications, MOSFETs need to demonstrate comparable noise performance. Although the channel thermal noise of MOSFET has been known to be the most dominant source of noise in the device, additional noise sources emerge as the CMOS technology scales down, such as gate tunneling current, and substrate noise. On the other hand, since the noise figure of the MOSFET decreases with technology scaling, HF noise measurement, and characterization of extremely small devices is becoming more challenging. Due to these challenges, there is a lot of research around new technologies, new materials and new devices. This chapter presents a review of some of the recent results in this exciting area.
2 citations
References
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TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations