scispace - formally typeset
Search or ask a question
Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI
TL;DR: In this paper, the Hot Wire (HW) Cell method was applied to grow epitaxial Si films at a substrate temperature of 200°C C 2 H 2 gas was added to this system and C containing epitaxia Si films were also obtained After annealing the films at 600-700°C, the vibration mode at 607 cm −1, which indicated the presence of the C atoms located at the Si substitutional sites, was observed in Fourier transform infrared absorption and Raman scattering spectroscopy.

2 citations

Fredrik Boxberg1
15 Aug 2007
TL;DR: In this article, the effect of elastic strain on the ballistic transport of electrons, in silicon electron wave guides; and on the electronic structure and photonic properties of III-V compound semiconductor heterostructures was investigated.
Abstract: The recent progress in microelectronic processing techniques has made it possible to fabricate artificial materials, dedicated and tailored directly for nanoelectronics and nanophotonics. The materials are designed to achieve a confinement of electrons to nanometer size foils or grains, often called quantum structures because of the quantization of the electron energies. In this work I have developed computationalmodels for the electronic structure, photonic recombination and carrier dynamics of quantum confined charge carriers of artificial materials. In this thesis I have studied in particular the effect of elastic strain on the ballistic transport of electrons, in silicon electron wave guides; and on the electronic structure and photonic properties of III-V compound semiconductor heterostructures. I have simulated two types of elastic strain. The strain in the silicon wave guides is induced by the thermal oxidation of the silicon processing and the strain of the III-V compound semiconductor structures is a result of a pseudomorphic integration of lattice mismatched materials. As one of the main results of this work, we have shown that the oxidation-induced strain can lead to current channeling effects in electron wave guides and a doubling of the conductance steps of the wave guide. In the case of the III-V compound semiconductor heterostructures, it was shown that piezoelectric potential (which is due to the elastic strain) complicates considerably the electron-hole confinement potential of strain-induced quantum dots. This has several consequences on the optical properties of these systems. Our results are well in agreement with experimental observations and do explain a set of experiments, which have so far lacked any explanation. This work does, thereby, imply a much better understanding of both silicon electron wave guides and strain-induced quantum dots. This could have implications for both further detailed experiments and future technological applications of the studied devices.

2 citations


Cites background from "Fabrication and analysis of deep su..."

  • ...in strained metal-oxide-semiconductor field effect transistors (MOSFETs) [17] and QW lasers....

    [...]

Proceedings ArticleDOI
01 Sep 2014
TL;DR: In this article, the average resistance of the transistors for finding the RC time constant and thereby the transient analysis of CMOS inverter circuits is calculated using simple yet efficient method.
Abstract: Rigorous mathematical formulation of digital circuits, although accurate, consumes simulation time of a circuit designer who wishes to have a quick investigation of the effect of various device parameters on the electrical response of a circuit This paper uses simple yet efficient method to calculate the average resistance of the transistors for finding the RC time constant and thereby the transient analysis of CMOS inverter circuits This method minimizes the computation time and reproduces the reported results We have investigated the effect of variation of different device parameters such as width, oxide thickness, length etc on the transient analysis of inverters Computations were carried out for strained/unstrained planar metal- oxide-semiconductor field-effect transistors (MOSFETs) and cylindrical gate-all-around (GAA) based CMOS inverters Voltage-transfer characteristics (VTC) have also been plotted Quantum effects have been incorporated for gate-all- around (GAA) MOSFETs based inverters

2 citations


Cites background from "Fabrication and analysis of deep su..."

  • ...kn(p) depends on the carrier relaxation time [18], [19] and strain [4]....

    [...]

  • ...To overcome the negative effects of device miniaturization, various techniques such as introduction of strain [3], [4], multi-gate [5], multi-channel [6]–[9] architectures are being investigated by the research community....

    [...]

Journal ArticleDOI
TL;DR: In this article, a low-temperature MOSFET process, in which all process temperatures after deposition of Si 1−y C y were lower than 800 °C, was developed and a strained Si 1 − y C y was fabricated.

2 citations

Journal ArticleDOI
TL;DR: In this article, a tensile (compressive)-strained channel is devised by the In0.52Al0.48As/In0.41Ga0.37As heterostructure.
Abstract: Comparative studies of double δ-doped InAlAs/InGaAs metal-oxide-semiconductor metamorphic high electron mobility transistors (MOS-MHEMTs) with different compressive-strained and tensile-strained channel structures have been made. In addition to the strain engineering of the heterostructure, the MOS-gate design is also integrated by using the cost-effective H2O2 oxidization technique. The tensile (compressive)-strained channel is devised by the In0.52Al0.48As/In0.41Ga0.59As (In0.52Al0.48As/In0.63Ga0.37As) heterostructure. Device characteristics with respect to different channel structures are physically studied. The impact-ionizationrelated kink effects in MHEMTs are significantly suppressed by the MOS-gate. Atomic force microscopy (AFM) and low-frequency noise (LFN) analysis were used to study the surface roughness and interface quality. As compared to the compressive-strained MOSMHEMT and conventional Schottky-gate devices, the present tensile-strained MOS-MHEMT design has demonstrated improved transconductance gain (gm), current drive, intrinsic voltage gain (AV), and power performance. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0031412jss] All rights reserved.

2 citations

References
More filters
Journal ArticleDOI
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...

1,500 citations

Journal ArticleDOI
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

1,389 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.

556 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

454 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

358 citations