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Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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Citations
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Journal ArticleDOI
TL;DR: In this paper, the impact of uniaxial strain and quantum mechanical effects on the threshold voltage of strained-Silicon nMOSFETs is studied by developing a physically-based model.
Abstract: Due to the large electron mobility gain cased by uniaxial stress along the [110] directions on (001) silicon substrate, in this paper, the impact of [110]/(001) uniaxial strain and quantum mechanical effects (QMEs) on the threshold voltage of strained-Silicon nMOSFETs is studied by developing a physically-based model. The impact of [110]/(001) stress on the band structure parameters such as density-of-state (DOS) in the conduction and valance band, band-gap and intrinsic carrier concentration is quantized first. Based on a modified threshold surface potential, the threshold voltage model is then proposed by solving the 2-D Poisson's equation and also by taking short channel effects, quantum effects and other secondary effects into consideration. Our analytical results agree with both TCAD and experimental data. The threshold voltage with the stress along arbitrary orientation can be analyzed analogously. This model can also be used for the design of nanoscale strained-Si nMOSFETs.

2 citations

Proceedings ArticleDOI
P. Waugh1
25 Aug 2008
TL;DR: In this paper, a series of Bragg Gratings were patterned on 1.5 micron SOI at Philips in Eindhoven to investigate the variation of grating parameters with a) the period of the gratings b) the duty cycle (or mark to space ratio) of the grating and c) the length of the region converted to Bragg gratings.
Abstract: The subject of this thesis is the design; analysis, fabrication and characterisation of first order Bragg Grating optical filters in Silicon-on-Insulator (SOI) planar waveguides. It is envisaged that this work will result in the possibility of Bragg Grating filters for use in Silicon Photonics. It is the purpose of the work to create as far as is possible flat surface waveguides so as to facilitate Thermo-Optic tuning and also the incorporation into rib-waveguide Silicon Photonics. The spectral response of the shallow Bragg Gratings was modelled using Coupled Mode Theory (CMT) by way of RSoft Gratingmod TM. Also the effect of having a Bragg Grating with alternate layers of refractive index 1.5 and 3.5 was simulated in order to verify that Silica and Silicon layered Bragg Gratings could be viable. A series of Bragg Gratings were patterned on 1.5 micron SOI at Philips in Eindhoven to investigate the variation of grating parameters with a) the period of the gratings b) the duty cycle (or mark to space ratio) of the gratings and c) the length of the region converted to Bragg Gratings (i.e. the number of grating period repetitions). One set of gratings were thermally oxidised at Philips in Eindhoven (this was to simulate the effects of oxidising Porous Silicon) and another set were ion implanted with Oxygen ions at the Ion Beam Facility, University of Surrey. The gratings were tested and found to give transmission minima at approximately 1540 nanometres and both methods of creating flat surfaces were found to give similar minima. Atomic Force Microscopy was applied to the grating area of the Ion as Implanted samples in the ATI, University of Surrey, which were found to have surface undulations in the order of 60 nanometres.

2 citations


Cites background from "Fabrication and analysis of deep su..."

  • ...551 Wavelength bmJ (3) If it is possible to create a more or less planar grating surface on the top of the rib of a SOI rib waveguide variable thermal tuning could be accomplished with the use of a control feedback heater to give a variable frequency Fabry-Perot effect....

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Journal ArticleDOI
TL;DR: In this article, the authors investigated the effect of the annealing temperature and the time on the bubble evolution on the hydrogen ion (H+)-implanted germanium (Ge) substrate.
Abstract: We investigate the effect of the annealing temperature and annealing time on the bubble evolution on the hydrogen ion (H+)-implanted germanium (Ge) substrate. It is found that the H2 aggregates gradually with the increase of the annealing time, and the aggregation rate of the H2 increases with the increase of the annealing temperature. Low-temperature Ge/Si wafer bonding (a-Ge interlayer) and Smart-Cut™ technique are applied to fabricate high-quality Ge-on-insulator (GOI). It is proved that thick Ge film is more difficult to be exfoliated from the Ge substrate. As long as the pressure in the bubbles is high enough, although the bubbles do not burst on the Ge surface, the lateral diffusion of H2 may occur to trigger the exfoliation of the Ge film. The contact of the wafers leads to the lateral merging of the small bubbles, resulting in the increase of the bubble size at the edge of the big void. It is believed that high bonding strength between Ge and SiO2 is essential to resist the high pressure in the bubble for the successful exfoliation of the Ge film. The point defects in the Ge film can be totally eliminated either by high-temperature annealing or by nanosecond pulse laser annealing, resulting in the improvement of the Ge film quality.

2 citations

Proceedings ArticleDOI
17 Dec 2010
TL;DR: In this paper, external compressive stresses were applied on a strained channel of n-p-MOSFETs and ROs in longitudinal and transverse configurations, and the authors proposed an approach to estimate parasitic capacitance shift under mechanical stress.
Abstract: This study proposes an approach to estimate parasitic capacitance shift under mechanical stress. The silicon-on-insulator n-/p- metal-oxide-semiconductor field-effect transistors (MOSFETs) and CMOS ring oscillators (ROs) were fabricated side by side in this study. External compressive stresses were applied on a strained channel of n-/p-MOSFETs and ROs in longitudinal and transverse configurations. The modeling mobilities of CMOS ROs used the measurement results of n-/p-MOSFET to simulate their oscillation frequencies under external stresses. The frequency difference between the experiment and simulation indicates parasitic capacitance variation under stresses.

2 citations


Cites background from "Fabrication and analysis of deep su..."

  • ...The mechanical stress-induced effects on metal-oxide­ semiconductor field-effect transistors (MOSFETs) have been intensively studied to determine an approach to increase the speed of these devices [1-10]....

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Journal ArticleDOI
TL;DR: In this paper, a real-space mapping of strain distributions in pseudomorphically strained, raised SiGe structures revealed that elastic relaxation extends approximately 20 times the feature thickness from their edges.
Abstract: The presence of strain distributions within semiconductor features influences many aspects of their behavior. For example, microelectronic technology that incorporates strained silicon improves device performance by increasing carrier mobility in the Si channels. Because current semiconductor fabrication contains multiple levels of metallic and dielectric structures, an understanding of the mechanical response of the constituent elements is critical to the prediction of the overall device performance. In addition, the interaction of strain fields between adjacent structures becomes greater as feature sizes decrease and the corresponding feature density increases. The use of synchrotron-based X-ray methods allows one to determine the interaction between strained features and their environment at a submicron resolution. Real-space mapping of strain distributions in pseudomorphically strained, raised SiGe structures revealed that elastic relaxation extends approximately 20 times the feature thickness from their edges. X-ray topographic methods were also applied to map the substrate deformation induced by overlying SiGe features. A formulation based on the classical Ewald-von Laue theory of dynamical diffraction was derived to match the measured diffraction profiles.

2 citations


Cites background from "Fabrication and analysis of deep su..."

  • ...The deposition of Si onto relaxed SiGe layers, which possess a larger lattice parameter, induces an isotropic, biaxial tensile strain, which improves electron mobility in NFET devices Rim et al., 2000 ....

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References
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Journal ArticleDOI
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...

1,500 citations

Journal ArticleDOI
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

1,389 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.

556 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

454 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

358 citations