Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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TL;DR: In this paper, the authors used the BSIM3 model for biaxially strained p-MOSFETs, using a proper parameter extraction method, to analyze the performance of several digital gates, including inverter, NAND, NOR, and static random access memory (SRAM) cells.
Abstract: Strain is one of the conventional methods used to enhance the mobility of carriers in metal–oxide–semiconductor field-effect transistors (MOSFETs). The strain is generated due to the lattice mismatch between the thin Si layer and underlying SiGe layers and reduces the effective mass of holes and inter-subband scattering. A compact model for such devices is essential to promote the design of very large-scale integration (VLSI) circuits using strained p-MOSFETs. In this paper, for the first time we propose to use the BSIM3 model for biaxially strained p-MOSFETs, using a proper parameter extraction method. The extracted model parameters are validated by comparing the results with technology computer-aided design (TCAD) simulations and a simple analytical model. The average error in the direct-current (DC) and alternating-current (AC) characteristics of the model is estimated to be below 1.5%. Finally, the extracted model is used to analyze the performance of several digital gates, including inverter, NAND, NOR, and static random-access memory (SRAM) cells, based on the strained p-MOSFET as a key circuit component. The simulation results show significant performance improvements of the gates in terms of the area, propagation delay, dynamic power consumption, static noise margin, and functional symmetry. By using strained p-MOSFETs in the SRAM cell, the active area of transistors can be reduced by up to 28.8% while at the same the time static power consumption is reduced by 4.8%, the static noise margin is increased by 10.5%, and the write access time is reduced by about 15.6%. These results not only suggest that the strained Si p-MOSFET can improve the performance of VLSI circuits but also confirm that the BSIM3 model with an appropriate parameter extraction method can be used for the design of digital circuits using strained p-MOSFETs.
1 citations
TL;DR: The dc operation of a simple current mirror built with two monolithically integrated strained-Si (s-Si) MOSFETs operating in the subthreshold region is studied as a function of temperature, highlighting the improved linearity and the threshold voltage stability in the s-Si circuit.
Abstract: The dc operation of a simple current mirror built with two monolithically integrated strained-Si (s-Si) MOSFETs operating in the subthreshold region is studied as a function of temperature. At room temperature, the log-log current relationship is linear over 4 dec. The consumed power is approximately 100 muW at 300 K but only 1 nW at 160 K. The cost of this reduction in power is a reduced linear log-log current range. Reducing the temperature further increases the threshold voltage, obstructing operation below 160 K. A comparison is made with the Si control circuit, highlighting the improved linearity and the threshold voltage stability in the s-Si circuit. The estimated cutoff frequency of the subthreshold strained-Si current mirror at 300 K is 50 MHz, compared to 10 kHz for the Si MOSFETs
1 citations
Cites background from "Fabrication and analysis of deep su..."
...STRAINED-Si (s-Si) MOSFETs have attracted a lot of interest lately because of their higher carrier mobility while retaining the conventional device MOSFET structure and fabrication technology [1]....
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05 Mar 2013
1 citations
26 Feb 2022
TL;DR: In this article , the authors presented the strained Si/relaxed Si0.8Ge0.2 heterostructure PMOS device with high k dielectric material using Silvaco ATLAS 2D simulator.
Abstract: The strained Si/relaxed Si0.8Ge0.2 heterostructure PMOS device with high k dielectric material is presented using Silvaco ATLAS 2D simulator in this paper. The electrical parameters like DIBL, subthreshold swing, transconductance, and ratio of on current to off current are analyzed and compared with the conventional strained Si/relaxed Si0.8Ge0.2 heterostructure PMOS device. In comparison to the strained Si/relaxed Si0.8Ge0.2 heterostructure PMOS device, the proposed device is found to be better one. A decrease of 20% DIBL has been reported in the proposed device and also the subthreshold swing (SS) value close to ideal one i.e., 60mV/decade.
1 citations
01 Jan 2011
TL;DR: In this article, an attempt has been made to model threshold voltage of biaxial strained silicon MOSFET in one dimension, and the results show that a significant amount of threshold voltage decrease has been observed with the increase in the germanium content in the silicon.
Abstract: In this paper, an attempt has been made to model threshold voltage of biaxial strained silicon MOSFET in one dimension. The results show that a significant amount of threshold voltage decrease has been observed with the increase in the germanium content in the silicon. The results have also been compared with the reported results. The results compare well with the existing reported work.
1 citations
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TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations