Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
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TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
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Proceedings ArticleDOI
Investigation of Si_3N_4 Capping Layer and Embedded SiGe Effect on 90 nm CMOS Devices
TL;DR: This paper highlights the effect of Si3N4 capping layer, embedded SiGe in the source/drain and SiGe layer on the bottom of the strained silicon for strained-silicon technology effect on 90 nm Complementary Metal Oxide Semiconductor (CMOS) performance focusing on threshold voltage and drain current parameters.
Journal ArticleDOI
The impact of germanium in strained si/relaxed si1-xge x on carrier performance in non-degenerate and degenerate regimes
Abstract: The impact of the fraction of germanium on the carrier performance of two-dimensional strained silicon, which embraces both the non-degenerate and degenerate regimes, is developed In this model, the Fermi integral of order zero is employed The impact of the fraction of germanium on the relaxed Si1−xGex substrate (x), carrier concentration and temperature is reported It is revealed that the effect of x on the hole concentration is dominant for a normalized Fermi energy of more than three, or in other words the non-degenerate regime On the contrary, the x gradient has less influence in the degenerate regime Furthermore, by increasing x there is an increase in the intrinsic velocity, particularly with high carrier concentration and temperature
Patent
Memory with strained semiconductor by wafer bonding with misorientation
TL;DR: In this article, at least two strong bonding regions are defined for a desired bond between a semiconductor membrane and a crystalline semiconductor substrate, separated by a weak bonding region.
Proceedings ArticleDOI
Simulation of nanoscale dual-channel strained Si/Strained Si 1−y Ge y /Relaxed Si 1−x Ge x PMOSFET
TL;DR: In this article, the effects of several parameters on the threshold voltage of nanoscale dual-channel Si/Strained Si 1−y Ge y /relaxed Si 1 −x Ge x PMOSFET are investigated using SILVACO TCAD tools.
Proceedings ArticleDOI
Comparison of DC, RF, and dispersion properties of SOI and strained-SOI N-MOSFETs
TL;DR: Results demonstrate that SSOI technology can improve f/sub t/ and f/ sub max/ conservatively by up to 50% without excessive dispersion/self-heating and measurements indicate that the SSOi wafer bonding process can produce an acceptable buried oxide interface trap density.
References
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Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI
On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI
Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.