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Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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Citations
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Proceedings ArticleDOI
01 Aug 2019
TL;DR: In this article, the shift of threshold voltage for Si-Si 1-x Gex heterostructure p-MOSFET is analytically evaluated for different substrate material composition.
Abstract: Shift of threshold voltage for Si-Si 1-x Gex heterostructure p-MOSFET is analytically evaluated for different substrate material composition. Poisson's equation is analytically solved subjected to practical range of tuning parameters and threshold is computed as a function of gate length in presence of body effect. Effect of High-K dielectric is calculated, and compared with that obtained for conventional SiO2 material. Result shows significant change of threshold in sub-micron gate length for different substrate compositions, as well as for high-K dielectrics, which can be effectively utilized for computing subthreshold current in presence of tunneling.

Cites background from "Fabrication and analysis of deep su..."

  • ...Short-channel effect is a long-standing problem which is already suggested solve by a variety of means, either by increasing number of gates [1-2], or by replacing the conventional dielectric [3-4] with high-K material, or by incorporating strained structure reinstating well-established substrate [5-6]....

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Book ChapterDOI
01 Jan 2015
TL;DR: This chapter begins with a brief review of the MOS structure, and lays the groundwork for the discussion of MOSFET characteristics in the sections that follow, with emphasis on key analog parameters.
Abstract: The trade-offs between parameters are different for digital, analog, and RF CMOS. In particular, there are conflicting requirements on operating voltage level, reduced low-frequency noise, high output resistance, low component mismatch, and high linearity between analog and digital CMOS. This requires modifications to be made to the basic digital structure to satisfy analog circuit needs. In contrast, the characteristics of RF CMOS are essentially the same as those of high-speed digital CMOS so that both designs can be integrated on the same chip with little added complexity. This chapter begins with a brief review of the MOS structure. This lays the groundwork for the discussion of MOSFET characteristics in the sections that follow, with emphasis on key analog parameters. The chapter concludes with a brief discussion of analog CMOS applications.
Proceedings ArticleDOI
07 Jul 2003
TL;DR: In this article, the SiO/sub x/N/sub y/Ta/sub 2/O/Sub 5/ gate stack is investigated as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained Si.
Abstract: In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.
Journal ArticleDOI
TL;DR: In this paper, alternative methods of improving transistor performance are investigated, such as reducing the critical dimensions of the transistors, which is becoming increasingly difficult to further reduce critical dimensions such as the gate oxide thickness.
Abstract: The amazing advancements achieved in Si CMOS have come primarily from scaling, i.e., from reducing the critical dimensions of the transistors. Since it is becoming increasingly difficult to further reduce critical dimensions such as the gate oxide thickness, alternative methods of improving transistor performance are being investigated.
Proceedings ArticleDOI
10 Dec 2002
TL;DR: In this paper, a high throughput SiGe UHV/CVD system is demonstrated, which is suitable for manufacture with the throughput of 14 200mm wafers per hour for the typical HBT structure.
Abstract: A high throughput SiGe UHV/CVD system is demonstrated. Due to the excellent uniformity of thickness and Ge concentration in within a wafer, wafer to wafer, and run-to-run, this system is suitable for manufacture with the throughput of 14 200-mm wafers per hour for the typical HBT structure. The UHV/CVD can fabricate low temperature Si, strained Si/sub 1-x/Ge/sub x/, strained Si/sub 1-x/Ge/sub x/ :C, Si/sub 1-y/C/sub y/, and relaxed SiGe buffers. Various devices with good performance are fabricated by the UHV/CVD system, including HBTs, heterojunction phototransistor, strained Si MOSFET, photodetectors, quantum dot photodetectors with 6-9 /spl mu/m responsivity, and strained SiGe MOSFET.
References
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Journal ArticleDOI
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...

1,500 citations

Journal ArticleDOI
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

1,389 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.

556 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

454 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

358 citations