Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
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TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
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Proceedings ArticleDOI
Impact of the scaling on the noise performance of deep-submicron Si/SiGe n-channel FETs
TL;DR: In this article, the authors present a simulation study of the thermal noise locally generated in the n-channel of strained-Si MOSFETs and compared the obtained results with those of a state-of-the-art 100 μm gate length bulk MOS-FET.
Journal ArticleDOI
Influence of Process Flow on the Characteristics of Strained-Si nMOSFETs
TL;DR: In this paper, the authors developed a process design that uses epitaxial growth of strained-Si layers after shallow trench isolation and well implantation to improve the drive current of n-type metal-oxide-semiconductor field effect transistors (nMOSFETs).
Journal ArticleDOI
Investigation of strain states and thermal stability of strained-Si-on-Insulator (sSOI) structures
TL;DR: In this paper, the in-plane and out-of-plane lattice constants were found not to change after annealing up to 1150°C with SiO2 films though those of thinner sSOI without the protection film gradually changed due to strain relaxation.
Proceedings ArticleDOI
Role of Body Effect on Threshold Voltage of Strained $\mathrm{Si}-\mathrm{Si}_{\mathrm{X}}\mathrm{Ge}_{1-\mathrm{X}}$ MOSFET
TL;DR: In this paper, the role of body effect coefficient on threshold voltage of Si/SiGe MOSFETs was analyzed and an optimized design criterion was evaluated for the minimum threshold under inversion condition.
References
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TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI
Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.