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Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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Citations
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Journal ArticleDOI
TL;DR: In this paper, an analytical relationship between the 2nd order mobility degradation factor and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ2 values from the literature.
Abstract: As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface-roughness scattering in silicon MOSFETs. This high-field mobility degradation is known to influence the harmonic distortion through higher order derivatives of the drain current. Failure to take these higher order derivatives into account can cause significant error in the predictive evaluation of linearity (VIP3) in MOSFETs. Electrical measurements are used to extract the 2nd order mobility degradation factor (θ2) from strained silicon MOSFETs fabricated on silicon germanium strain relaxed buffers with 15%, 20% and 25% germanium. Linearity and high-field mobility degradation are shown to be independent of strain in spite of atomic force microscopy measurements showing that the amplitude of the root-mean-square surface roughness increases with the germanium content. It is also shown that θ2 is required for accurate modelling of linearity. The impact of oxide thickness on linearity is also investigated through θ2. In this paper, an analytical relationship between θ2 and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ2 values from the literature. Using the extracted θ2 values as inputs to analytical MOSFET models, a correlation between the oxide thickness and linearity is analyzed.
Patent
29 Sep 2015
TL;DR: In this paper, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined, where the channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the straininducing regions of the isolation regions.
Abstract: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
Proceedings ArticleDOI
01 Oct 2004
TL;DR: In this paper, the authors investigated the thickness effect of silicon-germanium for surrounding-gate strained silicon nanowire FETs by their developed 3D nanodevice simulator, and found that a large R/sub SiGe/ increases the driving current and does almost not change the transfer characteristics.
Abstract: Strained silicon devices have been widely studied (Lee et al., 2002; Fenouillet-Beranger et al., 2004). They possess better driving capacity than that of silicon-based devices. Double-gate strained silicon field effect transistors (FET) have recently been proposed and found better transport characteristics than single gate strained devices. For example, double-gate strained silicon FETs not only have relatively high mobility, high transconductance, and ideal subthreshold swing but also suppress short-channel effects (SCEs) (Lee et al., 2002; Fenouillet-Beranger et al., 2004). Due to superior channel controllability, excellent performance of surrounding-gate FET has also been studied to further reduce SCEs (Yang et al., 2002; Venugopal et al., 2002); however, these structures have not been well investigated for strained silicon devices. We have investigated the thickness effect of silicon-germanium for surrounding-gate strained silicon nanowire FETs by our developed 3D nanodevice simulator. R/sub SiGe/ influences the driving current characteristic of surrounding-gate strained silicon nanowire FETs. A large R/sub SiGe/ increases the driving current and does almost not change the transfer characteristics. Strained silicon surrounding-gate nanowire FETs are numerically explored and optimized with respect to various physical parameters.
Patent
14 Apr 2004
TL;DR: In this article, the authors use the difference entre les coefficients de diffusion d'impuretes dans la couche de SiGe (2) and the couche of Si (3) to compare the concentration of impuretes in couche superieure and couche inferieure.
Abstract: Une pellicule semi-conducteur a structure en heterojonction, a savoir qu'une pellicule de semi-conducteur (11) est composee d'une couche de SiGe (2) et d'une couche de Si (3) sur la couche SiGe. En utilisant la difference entre les coefficients de diffusion d'impuretes dans la couche de SiGe (2) et la couche de Si (3), les concentrations d'impuretes sont controlees de sorte que la concentration des impuretes dans la couche superieure, c'est-a-dire la couche de SiGe (2) soit superieure a celle de la couche inferieure, c'est-a-dire la couche de Si (3). Le type de conductivite des impuretes dans la pellicule semi-conducteur (11) est a l'oppose du type de conductivite du transistor (c'est-a-dire, le type p si le transistor est de type n ou un type n si le transistor est un transistor MOS de type p). De cette maniere, un dispositif semi-conducteur ayant une structure de pression de compression et compose d'une couche semi-conducteur a structure en heterojonction possede une meilleure mobilite, des caracteristiques de transistor ameliorees et une haute fiabilite.
Journal ArticleDOI
TL;DR: In this article, a cross-sectional film specimen of Si/SiGe/Si on insulator was heated from room temperature up to 1113 K in high voltage transmission electron microscope (HVEM).
Abstract: Microstructural evolution is directly observed when the cross-sectional film specimen of Si/SiGe/Si on insulator (Si/SiGe/SOI) is heated from room temperature (R.T., 291 K) up to 1113 K in high voltage transmission electron microscope (HVEM). The misfit dislocation at the lower interface of the SiGe layer begins to extend downwards even at 913 K. The lower interface takes the lead in roughening against the upper interface of the SiGe layer. The roughened interface is ascribed to elastic relaxation. As misfit strain is partially transferred to SOI top Si layer and misfit dislocation is prolonged at the lower interface, the roughened interface turns smooth again. Thereafter, the misfit dislocations are introduced into the upper roughened interface of the SiGe layer to release the increased misfit strain. It is suggested that the microscopic relaxation of the SiGe layer is related to dislocation behavior and strain transfer.
References
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Journal ArticleDOI
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...

1,500 citations

Journal ArticleDOI
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

1,389 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.

556 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

454 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

358 citations