Fast algorithm for optimal layer assignment
Y. S. Kuo,T. C. Chern,Wei-Kuan Shih +2 more
- Iss: 3, pp 554-559
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TLDR
The authors propose a novel algorithm for optimal layer assignment under a general model where the planar graph has real-valued edge weights and the time complexity is O(n/sup 3/2/ log n) where n is the number of wire-segment clusters in a given layout.Abstract:
Given the geometry of wires for interconnections, the authors want to assign two conducting layers to the segments of these wires so that the number of vias required is minimized. This layer assignment problem, also referred to as the via minimization problem, has been formulated as finding a maximum cut of a planar graph. The authors propose a novel algorithm for optimal layer assignment under a general model where the planar graph has real-valued edge weights. The time complexity of the proposed algorithm is O(n/sup 3/2/ log n) where n is the number of wire-segment clusters in a given layout. In contrast, all existing optimal algorithms for layer assignment have the time complexity of O(n/sup 3/). >read more
Citations
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Proceedings ArticleDOI
Track assignment: a desirable intermediate step between global routing and detailed routing
TL;DR: This paper describes the intermediate track assignment problem and suggests an efficient heuristic for its solution and introduces cost metrics to model basic effects arising from connectivity and proposes a heuristic based on weighted bipartite matching as a core routine.
Journal ArticleDOI
An efficient approach to multilayer layer assignment with an application to via minimization
Chin-Chih Chang,Jason Cong +1 more
TL;DR: An efficient heuristic algorithm for the post-layout layer assignment and via minimization problem of multilayer gridless integrated circuit (IC), printed circuit board (PCB), and multichip module (MCM) layouts and how this algorithm can be used for delay and crosstalk minimization in high-performance IC, PCB, and MCM designs is outlined.
Proceedings ArticleDOI
An Efficient Multilayer MCM Router Based on Four-Via Routing
Kei-Yong Khoo,Jason Cong +1 more
TL;DR: An efficient multilayer general area router, named V4R, for MCM and dense PCB designs that combines global routing and detailed routing in one step and produces high quality detailed routing solutions directly from the given netlist and module placement.
Journal ArticleDOI
An efficient multilayer MCM router based on four-via routing
Kei-Yong Khoo,Jason Cong +1 more
TL;DR: The V4R as mentioned in this paper general area router combines global routing and detailed routing in one step and produces high quality detailed routing solutions directly from the given netlist and module placement using combinatorial optimization techniques, including efficient algorithms for computing a maximum weighted k-cofamily in a partially ordered set and a maximal weighted noncrossing matching in a bipartite graph, to solve the combined problem efficiently.
Journal ArticleDOI
Exact algorithms for multilayer topological via minimization
TL;DR: The authors show that if no local net exists in a channel, this problem is solvable in O(kn/sup 2/) time even for k layers, where n is the number of two-terminal nets.
References
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TL;DR: In this paper, it was shown that the vertices of a planar graph can be partitioned into three sets A, B, C such that no edge joins a vertex in A with another vertex in B, neither A nor B contains more than ${2n/3}$ vertices, and C contains no more than $2.
A separator theorem for planar graphs
TL;DR: In this paper, it was shown that the vertices of a planar graph can be partitioned into three sets A,B,C such that no edge joins a vertex in A with another vertex in B, neither A nor B contains more than 2n/3 vertices, and C contains no more than $2.