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Journal ArticleDOI

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

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TLDR
A unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions and results highlight the effectiveness of the proposed method in reducing test time.
Abstract
We present a unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions. We call an entire procedure, that delivers test packets to the subset of routers/cores, a test session. Test delivery for router/core testing is formulated as two fault-tolerant multicast algorithms. Test packet delivery for routers is implemented as a fault-tolerant unicast-based multicast scheme via the fault-free links and routers that were identified in the previous test sessions to avoid packet corruption. A new fault-tolerant routing algorithm is also proposed for the unicast-based multicast core test delivery in the whole network. Identical cores share the same test set, and they are tested within the same test session. Simulation results highlight the effectiveness of the proposed method in reducing test time.

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Citations
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Efficient Virtual Network Embedding of Cloud-Based Data Center Networks into Optical Networks

TL;DR: In this paper, the authors proposed a virtual network embedding (VNE) mathematical model used for optical data center networks and derived a priority of location VNE algorithm according to node proximity sensing and path comprehensive evaluation.
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Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks

TL;DR: In this paper, a test-time independent and optimally distributed test scheme named "Dugdugi" is proposed to address channel faults, e.g., short in an octagon and similar NoC architectures to achieve high reliability.
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An improved algorithm for accelerating reconfiguration of VLSI array

TL;DR: In this article, an efficient algorithm was proposed based on shortest path first principle for accelerating reconfiguration of VLSI processor subarrays with high power efficiency to meet the requirement of the power consumption of embedded system.
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An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray

TL;DR: This paper proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm, and proposed a multiple shortest augmenting path algorithm based on the new data structure which can significant reduce the running time.
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Reliability analysis of the cactus-based networks

TL;DR: In this article, the authors introduce a novel class of topological structure based on group theory, the n-dimensional cactus-based network, denoted by C N n, and show the characterization of algebraic and combinatorial properties for the cactus network as well as its connectivity.
References
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Journal ArticleDOI

Networks on chips: a new SoC paradigm

TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI

Route packets, not wires: on-chip interconnection networks

TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Journal ArticleDOI

An adaptive and fault tolerant wormhole routing strategy for k-ary n-cubes

TL;DR: The concept of virtual channels is extended to multiple virtual communication systems that provide adaptability and fault tolerance in addition to being deadlock-free, and virtual interconnection networks allowing adaptive, deadlocks-free routing are examined.
Journal ArticleDOI

Unicast-based multicast communication in wormhole-routed networks

TL;DR: Minimum-time multicast algorithms are presented for n-dimensional meshes and hypercubes that use deterministic, dimension-ordered routing of unicast messages, and can deliver a multicast message to m-1 destinations in [log/sub 2/ m] message passing steps, while avoiding contention among the constituent Unicast messages.
Journal ArticleDOI

Methods for fault tolerance in networks-on-chip

TL;DR: The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years.
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