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Proceedings ArticleDOI

FFT/IFFT implementation using Vivado™ HLS

24 May 2016-pp 1-2

TL;DR: A case study of using a high level synthesis tool for the design and implementation of an FFT core for use in a wireless modem that is competitive with the highly optimized IP core available from Xilinx for their FPGAs.
Abstract: High level synthesis tools are an attractive option for rapid prototyping and implementation of hardware designs. In this paper we present a case study of using such a tool for the design and implementation of an FFT core for use in a wireless modem. The optimizations used for directing the conversion of C code to hardware are discussed and the impact of the different directives is analyzed. The resulting hardware architecture is competitive with the highly optimized IP core available from Xilinx for their FPGAs in terms of the hardware requirements while achieving a slightly better latency for the same configuration.
Citations
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Journal ArticleDOI
Hongda Wang1, Weiwei Shi2, Chiu-Sing Choy1Institutions (2)
18 Sep 2018-IEEE Access
TL;DR: A real-time seizure detection algorithm based on STFT and support vector machine (SVM) and its field-programmable gate array (FPGA) implementation is proposed and the possibility of integrating the proposed algorithm and FPGA implementation into a wearable seizure control device is affirm.
Abstract: Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded as a promising alternative for surgical and drug treatment. In this paper, a real-time seizure detection algorithm based on STFT and support vector machine (SVM) and its field-programmable gate array (FPGA) implementation are proposed. With a two-stage patient-specific channel selection and feature selection mechanism, those redundant and uncorrelated spectral features are removed from the entire feature set. The evaluation results on CHB-MIT epilepsy database show that the mean detection latency of the proposed algorithm is 6 s, the sensitivity is 98.4%, and the false detection rate is 0.356/h. The performance of our proposed algorithm is comparable to other existing seizure detection algorithms. Moreover, we implement the proposed seizure detection algorithm on Xilinx Zynq-7000 XC7Z020 with high level synthesis. Each classification of the input electroencephalography signal can be finished within 313 $\mu \text{s}$ , and the power consumption of the programmable logic is only 380 mW at 100 MHz. In hardware implementation, an optimization strategy for the nested-loop structure within nonlinear SVM is proposed to improve pipeline efficiency. Compared with existing method, the experimental result shows that our method can speed up the nonlinear SVM by $1.70\times $ , $1.53\times $ , $1.37\times $ , and $1.26\times $ with the unroll factor equal to 1–4 at the same DSP utilization rate. The evaluation results affirm the possibility of integrating the proposed algorithm and FPGA implementation into a wearable seizure control device.

24 citations


Additional excerpts

  • ...Previous studies explored to utilize HLS for FFT design can be found in [40][41][45]....

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Proceedings ArticleDOI
Ghattas Akkad1, Ali Mansour1, Bachar El-Hassan2, Frederic Le Roy1  +1 moreInstitutions (3)
01 Nov 2018-
TL;DR: This study focuses on communication systems incorporating filter-based-multicarrier modulations (FBMC), a promising candidate for the 5G technology and implemented and tested various combinations using finite precision, HLS tools and HDL while prompting parallelization, pipelining and hardware reuse architectures.
Abstract: Fast Fourier Transform (FFT) is generally implemented on reconfigurable hardware in several signal processing or digital communication applications. It can be considered the most time and resource consuming operations due to the need of complex operations. The main of this manuscript is to investigate the contribution of High Level Synthesis (HLS) techniques on the implementation of real time FFT algorithms using field programmable gate arrays (FPGAs). In particular, this study focuses on communication systems incorporating filter-based-multicarrier modulations (FBMC), a promising candidate for the 5G technology. In order to evaluate the contribution of HLS, we implemented and tested various combinations such as: 8 and 16 points radix-2 and radix-4 FFT using finite precision, HLS tools and HDL while prompting parallelization, pipelining and hardware reuse architectures.

6 citations


Cites background or methods from "FFT/IFFT implementation using Vivad..."

  • ...In contrast, an HLS implementation is presented in [13] for FFT variants without its HDL counterpart....

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  • ...speed, resource utilization and latency, thus reducing development time by eliminating the need for recoding specific architectures [13]....

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Journal ArticleDOI
TL;DR: Comparison of simulation results from offline simulation tools with those from the proposed simulation system validates the correctness of the FPGA-based EMT simulation system using HLS technology.
Abstract: Field-programmable gate array (FPGA)-based simulation system is applied in real-time electromagnetic transient (EMT) simulation for small time-step simulation. However, the FPGA-based simulation system requires handcrafted hardware description language (HDL) and significant design efforts. This paper explores FPGA-based EMT real-time simulation system design using high-level synthesis (HLS) technology to accelerate the design process and improve the flexibility, because high-level language can be transferred into HDL using HLS. Furthermore, loop unroll and pipeline optimisation directives are analysed and applied for HLS to improve the computation speed of the components. The system can simulate various components, including switches, R-L-C, voltage sources, current sources, and transmission lines. Especially, the system adopting double-precision floating-point calculation can support the network with 74 nodes and achieve 2 us for each small time step on Xilinx Virtex7-690 T FPGA. Comparison of simulation results from offline simulation tools with those from the proposed simulation system validates the correctness of the FPGA-based EMT simulation system using HLS technology.

5 citations


Journal ArticleDOI
TL;DR: A dual threshold self-corrected minimum sum algorithm for low-density parity-check (LDPC) decoders is proposed, which erases unreliable messages, improving the decoding performance and efficiency of DT-SCMS.
Abstract: Fifth generation (5G) is a new generation mobile communication system developed for the growing demand for mobile communication. Channel coding is an indispensable part of most modern digital communication systems, for it can improve the transmission reliability and anti-interference. In order to meet the requirements of 5G communication, a dual threshold self-corrected minimum sum (DT-SCMS) algorithm for low-density parity-check (LDPC) decoders is proposed in this paper. Besides, an architecture of LDPC decoders is designed. By setting thresholds to judge the reliability of messages, the DT-SCMS algorithm erases unreliable messages, improving the decoding performance and efficiency. Simulation results show that the performance of DT-SCMS is better than that of SCMS. When the code rate is 1/3, the performance of DT-SCMS has been improved by 0.2 dB at the bit error rate of 10 − 4 compared with SCMS. In terms of the convergence, when the code rate is 2/3, the number of iterations of DT-SCMS can be reduced by up to 20.46% compared with SCMS, and the average proportion of reduction is 18.68%.

References
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Journal ArticleDOI
Jason Cong, Bin Liu, Stephen Neuendorffer1, Juanjo Noguera1  +2 moreInstitutions (1)
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Abstract: Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

636 citations


"FFT/IFFT implementation using Vivad..." refers background in this paper

  • ...In high level synthesis (HLS), a description written in high level language such as C is automatically converted to RTL in a hardware description language (HDL) such as Verilog or VHDL....

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  • ...I. INTRODUCTION Increase in the design complexity has encouraged the design automation community to look at higher level of abstraction than register transfer level (RTL) [1]....

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  • ...INTRODUCTION Increase in the design complexity has encouraged the design automation community to look at higher level of abstraction than register transfer level (RTL) [1]....

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Journal ArticleDOI
Grant Martin1, G. SmithInstitutions (1)
TL;DR: The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.
Abstract: This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.

286 citations


"FFT/IFFT implementation using Vivad..." refers background in this paper

  • ...There have been many attempts at high level synthesis [2]....

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Journal ArticleDOI
TL;DR: This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis using HLS tools and Fast Fourier Transform implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware.
Abstract: This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools. Hence, in order to demonstrate the fundamental hardware design concepts, a case studyis presented. Fast Fourier Transform (FFT) implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware using HLS tools. There are additional language constraints that need to be addressed including use of pointers, recursion and floating point types.

14 citations


"FFT/IFFT implementation using Vivad..." refers methods in this paper

  • ...The FFT implementation using PICO tool [6] is able to perform N point FFT in N+ 32Nlog2N+N cycles for 1024 point FFT at 270MHz....

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