Finding all simple disjunctive decompositions using irredundant sum-of-products forms
01 Nov 1998-pp 111-117
TL;DR: It is proved that all simple disjunctive decompositions can be extracted in the method, namely all possible decomposition are included in the factored logic networks.
Abstract: Finding disjunctive decompositions is an important technique to realize compact logic networks Simple disjunctive decomposition is a basic and useful concept, that extracts a single output subblock function whose input variable set is disjunctive from the other part The paper presents a method for finding simple disjunctive decompositions by generating irredundant sum-of-products forms and applying factorization We prove that all simple disjunctive decompositions can be extracted in our method, namely all possible decompositions are included in the factored logic networks Experimental results show that our method can efficiently extract all the simple disjunctive decompositions of the large scale functions Our result clarifies the relationship between the functional decomposition method and the two-level logic factorization method
Citations
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22 Jun 2001
TL;DR: Experimental results over MCNC benchmarks show that this approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time.
Abstract: We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don't-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists are provably non-redundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time.
105 citations
01 Nov 2001
TL;DR: The application of BDDs offers an increased computational efficiency and makes them an attractive alternative to algebraic methods for multi-level logic optimization, namely algebraic logic optimisation, Boolean logic optimization and decomposition as mentioned in this paper.
Abstract: Three basic methods for multi-level logic optimization, namely algebraic logic optimization, Boolean logic optimization, and decomposition is a fundamental technology for the generation of multi-level logic. The application of BDDs offers an increased computational efficiency and makes them an attractive alternative to algebraic methods. These three methods are key technologies for state-of-the-art logic synthesis tools.
18 citations
23 May 2004
TL;DR: First, it is proved that there exists an algorithm for computing all multiple-vertex dominators of a fixed size in polynomial time, and then it is shown that the problem of computing non-disjoint decompositions of Boolean functions can be reduced to the issue of finding multiple- Vertex dominator of circuit graphs.
Abstract: This paper addresses the problem of non-disjoint decomposition of Boolean functions. Decomposition has multiple applications in logic synthesis, testing and formal verification. First, we show that the problem of computing non-disjoint decompositions of Boolean functions can be reduced to the problem of finding multiple-vertex dominators of circuit graphs. Then, we prove that there exists an algorithm for computing all multiple-vertex dominators of a fixed size in polynomial time. Our result is important because no polynomial-time algorithm for non-disjoint decomposition of Boolean functions is known. A set of experiments on benchmark circuits illustrates our approach.
15 citations
Cites background from "Finding all simple disjunctive deco..."
...[19] S. Minato and G. De Micheli, “Finding all simple disjunctive decompositions using irredundant sum-of-products forms,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 111–117....
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...Minato and De Micheli [19] presented an algorithm which computes all disjoint decompositions by generating irreducible sum-of-product for the function from its BDD and applying factorization....
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27 Mar 2017
TL;DR: This paper found a special property of index generation functions that drastically reduces this search space for finding an optimum support-reducing decomposition, and developed a fast algorithm that finds a decomposition with the fewest rails.
Abstract: Index generation functions are useful for pattern matching. This paper presents an algorithm to find support-reducing decompositions for index generation functions. Let n be the number of the input variables, and let s be the number of bound variables. Then, the exhaustive search for finding an optimum support-reducing decomposition requires to check (n s ) combinations. We found a special property of index generation functions that drastically reduces this search space. With this property, we developed a fast algorithm. For a given number of bound variables, it finds a decomposition with the fewest rails. Experimental results up to n = 60 and s = 33 are shown.
14 citations
Cites methods from "Finding all simple disjunctive deco..."
...For the decomposition with r = 1, efficient algorithms using BDDs [2], [5], and SOP [7] are available....
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Dissertation•
09 Oct 2006
TL;DR: Novel heuristic algorithms for functional decomposition are presented which can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering.
Abstract: Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing.
This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient.
The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering.
The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time.
The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function.
The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches.
Finally we present two publications that resulted from the many detours we have taken along the winding path of our research.
11 citations
References
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TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Abstract: In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach.
9,021 citations
Book•
31 Aug 1984
TL;DR: The ESPRESSO-IIAPL as discussed by the authors is an extension of the ESPRSO-IIC with the purpose of improving the efficiency of Tautology and reducing the number of blocks and covers.
Abstract: 1. Introduction.- 1.1 Design Styles for VLSI Systems.- 1.2 Automatic Logic Synthesis.- 1.3 PLA Implementation.- 1.4 History of Logic Minimization.- 1.5 ESPRESSO-II.- 1.6 Organization of the Book.- 2. Basic Definitions.- 2.1 Operations on Logic Functions.- 2.2 Algebraic Representation of a Logic Function.- 2.3 Cubes and Covers.- 3. Decomposition and Unate Functions.- 3.1 Cofactors and the Shannon Expansion.- 3.2 Merging.- 3.3 Unate Functions.- 3.4 The Choice of the Splitting Variable.- 3.5 Unate Complementation.- 3.6 SIMPLIFY.- 4. The ESPRESSO Minimization Loop and Algorithms.- 4.0 Introduction.- 4.1 Complementation.- 4.2 Tautology.- 4.2.1 Vanilla Recursive Tautology.- 4.2.2 Efficiency Results for Tautology.- 4.2.3 Improving the Efficiency of Tautology.- 4.2.4 Tautology for Multiple-Output Functions.- 4.3 Expand.- 4.3.1 The Blocking Matrix.- 4.3.2 The Covering Matrix.- 4.3.3 Multiple-Output Functions.- 4.3.4 Reduction of the Blocking and Covering Matrices.- 4.3.5 The Raising Set and Maximal Feasible Covering Set.- 4.3.6 The Endgame.- 4.3.7 The Primality of c+.- 4.4 Essential Primes.- 4.5 Irredundant Cover.- 4.6 Reduction.- 4.6.1 The Unate Recursive Paradigm for Reduction.- 4.6.2 Establishing the Recursive Paradigm.- 4.6.3 The Unate Case.- 4.7 Lastgasp.- 4.8 Makesparse.- 4.9 Output Splitting.- 5. Multiple-Valued Minimization.- 6. Experimental Results.- 6.1 Analysis of Raw Data for ESPRESSO-IIAPL.- 6.2 Analysis of Algorithms.- 6.3 Optimality of ESPRESSO-II Results.- 7. Comparisons and Conclusions.- 7.1 Qualitative Evaluation of Algorithms of ESPRESSO-II.- 7.2 Comparison with ESPRESSO-IIC.- 7.3 Comparison of ESPRESSO-II with Other Programs.- 7.4 Other Applications of Logic Minimization.- 7.5 Directions for Future Research.- References.
1,347 citations
TL;DR: An overview of the MIS system and a description of the algorithms used are provided, including some examples illustrating an input language used for specifying logic and don't-cares.
Abstract: MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.
1,139 citations
"Finding all simple disjunctive deco..." refers methods in this paper
...We compared the number of literals in nal SOP networks with other optimizers LODE[5] and SIS[3]....
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...Irredundant SOPs can also be obtained by other algorithms, such as ESPRESSO[2] or simplify command in SIS[3], however, those algorithms do not satisfy the Condition 3....
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TL;DR: A general approach to functional decomposition is given and efficient tests for the detection of decompositions are derived and these results are employed in the development of an alphabetic search procedure for determining minimum-cost Boolean graphs which satisfy any given design specifications.
Abstract: This paper presents a systematic procedure for thed esign of gate-type combinational switching circuits without diredted loops. Each such circuit (Boolean graph) is in correspondence with a sequence of decompositions of the Boolean function which it realizes. A general approach to functional decomposition i s given and, in terms oaf convenient positional representation, efficient tests for the detection of decompositions are derived. These results are employed in the development of an alphabetic search procedure for determining minimum-cost Boolean graphs which satisfy any given design specifications.
242 citations
01 Jul 1993
TL;DR: A theory for (disjunctive and nondisjunctive) function decomposition using the BDD representation of Boolean functions and a novel algorithm for generating the set of all bound variables that make the function decomposable is presented.
Abstract: This paper presents a theory for (disjunctive and nondisjunctive) function decomposition using the BDD representation of Boolean functions. Incompletely specified as well as multi-output Boolean functions are addressed as part of the general theory. A novel algorithm (based on an EVBDD representation) for generating the set of all bound variables that make the function decomposable is also presented. We compared our BDD-based decomposition procedure with existing implementations of the Roth-Karp procedure and obtained significant speed-ups.
140 citations