FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics
TL;DR: In this article, the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics were analyzed.
Abstract: This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-fe metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO2 and SiO2/HfO2) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM.
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TL;DR: In this article, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated, and the ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL).
114 citations
24 Mar 2014
TL;DR: A comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell reveals that 8T cell degrades 1.31× faster than 6T cell, and that FinFet cells are more vulnerable to BTI degradation than planar CMOS cells.
Abstract: Bias Temperature Instability (BTI) is posing a major reliability challenge for today's and future semiconductor devices as it degrades their performance. This paper provides a comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell. The evaluation metrics are read Static Noise Margin (SNM), hold SNM and Write Trip Point (WTP); while the aspects investigated include BTI impact dependence on the supply voltage, cell strength, and design styles (6 versus 8 Transistors cell). A comparison between FinFET and planar CMOS based SRAM cells degradation is also covered. The simulation performed on FinFET based cells for 108 seconds of operation under nominal Vdd show that Read SNM degradation is 16.72%, which is 1.17X faster than hold SNM, while WTP improves by 6.82%. In addition, a supply voltage increment of 25% reduces the Read SNM degradation by 40%, while strengthening the cell pull-down transistors by 1.5× reduces the degradation by only 22%. Moreover, the results reveal that 8T cell degrades 1.31× faster than 6T cell, and that FinFET cells are more vulnerable (~ 2×) to BTI degradation than planar CMOS cells.
55 citations
Cites background from "FinFET SRAM Cell Optimization Consi..."
...On the other hand, few authors have focused on the BTI analysis of FinFET based devices [3,4,11]....
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Patent•
TSMC1
TL;DR: In this article, static random access memory (SRAM) cells and SRAM cell arrays are disclosed, and a pull-up transistor includes a Fin field effect transistor (FinFET) with a fin of semiconductive material.
Abstract: Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.
52 citations
TL;DR: In this paper, the statistical variability of the static noise margin of a six-transistor bulk complementary metal-oxide-semiconductor static random access memory (SRAM) cell due to random doping fluctuations (RDFs) was investigated via 3-D technology computer-aided design simulations.
Abstract: The statistical variability of the static noise margin of a six-transistor bulk complementary metal-oxide-semiconductor static random access memory (SRAM) cell due to random doping fluctuations (RDFs) is investigated via 3-D technology computer-aided design simulations The SRAM cell is created through 3-D process simulations of the entire cell as a single structure The process flow is based on a typical 32-nm technology The effects of RDFs on the cell performance are investigated using the highly efficient statistical impedance field method
30 citations
Cites background from "FinFET SRAM Cell Optimization Consi..."
...In [5], 3-D technology computer-aided design (TCAD) simulations for an entire...
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Patent•
30 Oct 2014TL;DR: In this article, an improved finFET and method of fabrication is disclosed, which takes advantage of the different epitaxial growth rates of {110} and {100} silicon.
Abstract: An improved finFET and method of fabrication is disclosed Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls) The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit
27 citations
References
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IBM1
TL;DR: In this article, the authors generalized the energy-level calculation to include arbitrary orientations of the constant energy ellipsoids in the bulk, the surface or interface, and an external magnetic field.
Abstract: The strong surface electric field associated with a semiconductor inversion layer quantizes the motion normal to the surface. The bulk energy bands split into electric sub-bands near the surface, each of which is a two-dimensional continuum associated with one of the quantized levels. We treat the electric quantum limit, in which only the lowest electric sub-band is occupied. Within the effective-mass approximation, we have generalized the energy-level calculation to include arbitrary orientations of (1) the constant-energy ellipsoids in the bulk, (2) the surface or interface, and (3) an external magnetic field. The potential associated with a charged center located an arbitrary distance from the surface is calculated, taking into account screening by carriers in the inversion layer. The bound states in the inversion layer due to attractive Coulomb centers are calculated for a model potential which assumes the inversion layer to have zero thickness. The Born approximation is compared with a phase-shift calculation of the scattering cross section, and is found to be reasonably good for the range of carrier concentrations encountered in InAs surfaces. The low-temperature mobility associated with screened Coulomb scattering by known charges at the surface and in the semiconductor depletion layer is calculated for InAs and for Si (100) surfaces in the Born approximation, using a potential that takes the inversion-layer charge distribution into account. The InAs results are in good agreement with experiment. In Si, but not in InAs, freeze-out of carriers into inversion-layer bound states is expected at low temperatures and low inversion-layer charge densities, and the predicted behavior is in qualitative agreement with experiment. An Appendix gives the phase-shift method for two-dimensional scattering and the exact cross section for scattering by an unscreened Coulomb potential.
1,468 citations
"FinFET SRAM Cell Optimization Consi..." refers background in this paper
...Due to the difference in quantization effective mass [18]–[20], the effect of quantum confinement varies for different orientations....
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TL;DR: A comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model is constructed and it is demonstrated how to solve the reaction-diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work.
710 citations
"FinFET SRAM Cell Optimization Consi..." refers methods in this paper
...Reaction–diffusion model [14] is used to calibrate the threshold voltage drift due to NBTI/PBTI [10], [15]....
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01 Jan 2009
TL;DR: Although the operation time was not significantly decreased, patients without drainage could save much more time and money and simultaneously reach similar postoperative effects in psychosocial well-being, sexual well- Being, physical well- being, and satisfaction with breasts.
Abstract: To explore the necessity of indwelling drainage in dual-plane breast augmentation mammoplasty patients. Female patients (123 in total) were selected from June 2015 to June 2018 in the Department of Plastic Surgery at Peking Union Medical College Hospital and were randomly divided into 2 different groups: the with drainage group (WD group, 57 patients) and the without drainage group (WOD group, 66 patients). In the 2 groups, the operation time, postoperative stay, and hospitalization expenses were recorded. The BREAST-Q Version 2.0 Augmentation Module Preand Postoperative Scales (Chinese Version) were used to evaluate psychosocial well-being, sexual well-being, physical well-being, and satisfaction with breasts preoperatively and postoperatively (1 year after operation). Before the operation, no significant differences were found in psychosocial well-being, sexual well-being, physical well-being, or satisfaction with breasts between these 2 groups. In the WOD group, postoperative stay and hospitalization expenses were remarkably decreased, but the operation time was similar, compared with the WD group. Compared with before the operation, both groups had significantly increased scores in psychosocial well-being, sexual well-being, and satisfaction with breasts after the operation. However, no significant differences were found between the 2 groups. No complications were found in any of the patients. Although the operation time was not significantly decreased, patients without drainage could savemuchmore time andmoney and simultaneously reach similar postoperative effects in psychosocial well-being, sexual well-being, physical well-being, and satisfaction with breasts. Therefore, drainage may not be necessary in patients who undergo dual-plane breast augmentation mammoplasty. Abbreviations: CN = Chinese, SD = standard deviation, WD = with drainage, WOD = without drainage.
624 citations
TL;DR: In this paper, the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs was investigated.
Abstract: In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.
612 citations
"FinFET SRAM Cell Optimization Consi..." refers methods in this paper
..., fin LER [4], [16], the rough line edge patterns are generated using Fourier synthesis approach [17] with correlation length = 20 nm and Fig....
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IBM1
TL;DR: In this paper, the authors present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials, including SiO 2/NiSi and SiO2/HfO2 devices with TiN and Re as gates.
Abstract: Threshold voltage (Vt) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V t shift is an important transistor reliability issue. Vt shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO2 SiO2/HfO2 and SiO2/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO 2/NiSi and SiO2/HfO2/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO2/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO 2/HfO2/TiN and SiO2/HfO2/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO2 devices is much smaller than those observed for SiO2/HfO2/NiSi. In summary for SiO2/HfO2 stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO2 FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO2/FUSI FETs
219 citations
"FinFET SRAM Cell Optimization Consi..." refers methods in this paper
...Reaction–diffusion model [14] is used to calibrate the threshold voltage drift due to NBTI/PBTI [10], [15]....
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