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Journal ArticleDOI

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

TL;DR: In this article, the design space, including fin thickness, fin height, fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints.
Abstract: In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with Tfin = 10 nm and Hfin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.
Citations
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Journal ArticleDOI
TL;DR: Research on FinFETs from the bottommost device level to the topmost architecture level is reviewed and various possible FinFet asymmetries and their impact are surveyed, and novel logic-level and architecture-level tradeoffs offered by FinFetts are surveyed.
Abstract: Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

142 citations

Proceedings ArticleDOI
Geoffrey Yeap1
01 Dec 2013
TL;DR: For mobile SoCs to continue offering new and exciting user-experiences, and longer battery life, a holistic approach in orthogonal system scaling to break out of the box of (speed*density/power/cost) constrains is mandated.
Abstract: The explosive growth of smart mobile wireless devices in recent years has fundamentally transformed the semiconductor industry. Mobile system-on-chips (SoCs) has become the leading product driver for technology definition and manufacturing for the semiconductor industry. This trend was first observed in 28 nm and will continue for 20 nm, 16/14 nm, and 10 nm adoption and production ramp. Recent mobile SoC performance increase was achieved mainly through silicon technology scaling, and from single to dual- and quad-core. For mobile SoCs to continue offering new and exciting user-experiences, and longer battery life, a holistic approach in orthogonal system scaling to break out of the box of (speed*density/power/cost) constrains is mandated. Examples in the new paradigm of mobile heterogeneous computing are: energy-efficient transistors/memories/interconnects in expanding and boosting existing SoC functionalities (e.g., SiGe/III-V FinFET, GAA-FET, TFET, and RRAM/MRAM etc.), all-inclusive technology/design co-optimization to extract more values from silicon tech, RFFE system integration, and the multi-die integration by system partitioning that allows each component to be optimized and integrated closely together for lower cost and power, higher performance, and reduced form factor. Numerous challenges are ahead yet tremendous opportunities exist for collaborative and multiplicative innovations in the industry to enable the continued growth of mobile SoCs.

61 citations

Journal ArticleDOI
TL;DR: In this paper, the effect of fin width downscaling on hole and electron mobility behavior in FinFETs with (1, 0, 0) and (1, 1, 1) oriented sidewalls is examined, and the suitability of well-calibrated EMA for the simulation of hole mobility is confirmed.
Abstract: Influence of fin width downscaling on hole and electron mobility behavior in FinFETs with (1 0 0), (1 1 0) and (1 1 1) oriented sidewalls is examined. Our effective-mass model reproduces experimental results of UTB SOI pMOSFETs fabricated on (1 0 0) and (1 1 0) surfaces, including the effect of mobility enhancement for certain body thicknesses in (1 1 0) oriented devices. The suitability of well-calibrated EMA for the simulation of hole mobility is confirmed by our results, which opens a possibility of using hole EMA in advanced Monte Carlo simulators. Simulations show that with the downscaling of fin width nFinFETs with (1 0 0) sidewalls and pFinFETs with (1 1 0) and (1 1 1) sidewalls exhibit mobility enhancement in certain fin-width ranges. In contrast, other FinFET configurations experience monotonic mobility degradation with the decreasing fin width. Regarding experimental (1 1 1) FinFETs from our previous work, modeling results suggest that the fin width is highly uniform along the channel, both in nFinFETs and pFinFETs. The impact of electron and hole mobility behavior in UTB FinFETs on SRAM design is also studied. We have found that FinFETs with (1 1 1) active surface enable the most efficient use of the layout area, demanding only four fins for an SRAM cell with matched inverters and high immunity to noise.

16 citations

Proceedings ArticleDOI
29 Apr 2013
TL;DR: This paper investigates the fault behaviors of the gate oxide short in FinFETs using TCAD mixed-mode simulations and proposes two new test methods that prove the two methods' test efficacy of detecting the Gate oxide shorts uncovered by traditional test methods.
Abstract: When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.

13 citations


Cites background from "FinFET SRAM Optimization With Fin T..."

  • ...This is because FinFET possesses the superior electrical characteristics such as reduced short channel effect, good sub-threshold slope, reduced random dopant fluctuation [1] [2], and high-speed performance [3]....

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Journal ArticleDOI
TL;DR: Simulation results at 32 nm FinFET process show that the proposed design is capable of maintaining high noise immunity at all process corners and a constant performance in the presence of systematic as well as random process and temperature variations.
Abstract: With continued scaling of VLSI circuits, reliability has emerged out as one of the major circuit design challenges. Systematic die-to-die, random on-die as well as temperature and supply voltage variations are major sources of performance degradation which leads to unreliable circuits. Further, with reduced short channel effects at highly scaled nodes, the FinFET has recently been emerged as a suitable replacement of CMOS in the VLSI industry. Wide fan-in FinFET domino logic OR gate is one such circuit, which serves as an integral part of register file in a high-speed FinFET microprocessor. This circuit inherently suffers from low noise immunity which get worsens with circuit parameter variations due to process and temperature variations. At highly scaled technology nodes, it has been studied that the effects of on-die random process variation surpass the effects of systematic variations. Furthermore, at deep sub-nanometer scale the effect of process variation on device parameters is higher in FinFET as compared to CMOS. In this research work a reliable current mirror-based wide fan-in FinFET domino OR gate is proposed for temperature, random on-die and systematic die-to-die process variation tolerance. Simulation results at 32 nm FinFET process show that the proposed design is capable of maintaining high noise immunity (Unity Noise Gain of nearly 0.4 V) at all process corners and a constant performance (with reduced delay by 30% as compared to conventional design) in the presence of systematic as well as random process and temperature variations.

11 citations

References
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Journal ArticleDOI
E. Seevinck1, F.J. List1, J. Lohstroh1
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Abstract: The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

1,456 citations


"FinFET SRAM Optimization With Fin T..." refers methods in this paper

  • ...The RSNM and the WNM are measured with the methods described in [18] and [19], respectively....

    [...]

Proceedings ArticleDOI
01 Jan 2002
TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.
Abstract: While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

611 citations


"FinFET SRAM Optimization With Fin T..." refers background in this paper

  • ...The Hfin and Tfin ratio depends on the technology constraint and is generally chosen to be 1–5 [15]....

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Proceedings ArticleDOI
01 Dec 1999
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Abstract: High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

550 citations

Journal ArticleDOI
TL;DR: A methodology to statistically design the SRAM cell and the memory organization using the failure-probability and the yield-prediction models and can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.
Abstract: In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.

494 citations

Proceedings ArticleDOI
K. Kuhn1
01 Dec 2007
TL;DR: In this article, the authors present an overview of process variation effects, including examples of mitigation strategies and test methods for 45 nm and 65 nm RDFs, including SRAM matching and interconnect variation.
Abstract: This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45 nm and 65 nm RDF. SRAM matching and interconnect variation is discussed for both 65 nm and 45 nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65 nm and 45 nm products.

328 citations


"FinFET SRAM Optimization With Fin T..." refers methods in this paper

  • ...76 mV · μm are used for the Avt of the planar device and FinFET, respectively [17]....

    [...]