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Flit Synchronous Aelite Network on Chip
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TLDR
The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements and implements flit synchronous communication using mesochronous and asynchronous links.Abstract:
The deep sub micron process technology and application convergence increases the design challenges in System-on-Chip (SoC). The traditional bus based on chip communication are not scalable and fails to deliver the performance requirements of the complex SoC. The Network on Chip (NoC) has been emerged as a solution to address these complexities of a efficient, high performance, scalable SoC design. The Aethereal NoC provides the latency and throughput bounds by pipelined timedivision multiplexed (TDM) circuit switching architecture. A global synchronous clock defines the timing for TDM, which is not beneficial for decreasing process geometry and increasing clock frequency. This thesis work focuses on the Aelite NoC architecture. The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements. The Aelite NoC implements flit synchronous communication using mesochronous and asynchronous links.read more
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Book ChapterDOI
Zooming in on network-on-chip architectures
TL;DR: A new classification of chip architectures into three categories with different requirements from their NoCs is presented, to stimulate some research directions, and several research problems arising in these categories such as routing, quality-of-service, flow and congestion control, and resource allocation are highlighted.
Proceedings ArticleDOI
Skew Insensitive Physical Links for Network on Chip
Daniele Mangano,Riccardo Locatelli,Alberto Scandurra,Carlo Pistritto,Marcello Coppola,Luca Fanucci,Francesco Vitullo,Dario Zandri +7 more
TL;DR: Two architectures of advanced physical link for NoC, the former based on mesochronous technology, the latter based on asynchronous, are described.
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NoC design flow for TDMA and QoS management in a GALS context
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Proceedings ArticleDOI
Low power sequential circuit design by using priority encoding and clock gating
Xunwei Wu,Massoud Pedram +1 more
TL;DR: In this article, a state assignment technique called priority encoding is presented, which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits, which can result in sizable power saving.
Proceedings ArticleDOI
Multi-clock driven system: a novel VLSI architecture
TL;DR: This paper presents an asynchronous solution for VLSI system design that has several advantages such as low fan-out of clock signals, low power dissipation, and flexibility for different delay times.
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