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Journal ArticleDOI

Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs

22 Jul 2003-IEEE Electron Device Letters (IEEE)-Vol. 24, Iss: 6, pp 414-416
TL;DR: In this paper, the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs was investigated, and it was shown that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance.
Abstract: This paper investigates the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs. It is shown for the first time that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance. It is demonstrated that the appearance of these transitions, the position and amplitude of which strongly depend on the substrate doping, is caused by the variation of the potential at substrate-buried oxide interface, which we call the Floating Effective Back-Gate (FEBG) effect. A first-order small-signal equivalent circuit is proposed to support our observations.
Citations
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Journal ArticleDOI
TL;DR: In this article, a 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs.
Abstract: This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability

128 citations

Journal ArticleDOI
TL;DR: In this paper, the authors characterized the dynamic self-heating effect in n-channel SOI FinFETs, and the dependence of thermal resistance on finFET geometry is discussed.
Abstract: Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.

81 citations


Cites background from "Floating effective back-gate effect..."

  • ...The first transition occurs at low frequencies (1–100 Hz) and is due to the relaxation of the minority carriers in the Si substrate [17], [18]....

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  • ...The inertia of the majority carriers in the substrate causes the output conduction variation at frequencies of a few hundred megahertz [17], [18] for a standard resistivity SOI substrate (∼20 Ω · cm)....

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Journal ArticleDOI
TL;DR: UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150-220 GHz.
Abstract: In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150-220 GHz. Effect of operation regime, substrate bias, channel width and high temperature (up to 250 °C) on analog figures-of-merit (FoM) are analyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented.

46 citations

Journal ArticleDOI
TL;DR: In this article, a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements is presented, and the technique of determining isothermal condition using only the selfheating (thermal) dominated range of the spectrum.
Abstract: In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.

42 citations


Cites background from "Floating effective back-gate effect..."

  • ...In advanced MOSFETs, this frequency is so high that substrate and gate resistance network comes into picture [9]–[12], and gDS does not show any plateau in the frequency range of interest which makes self-heating time constant characterization difficult in most of the existing methods....

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Journal ArticleDOI
TL;DR: In this paper, the frequency variation of the output conductance in ultra-thin body with ultra thin BOX (UTBB) SOI MOSFETs without a ground plane is studied through measurements and two-dimensional simulations.
Abstract: The frequency variation of the output conductance in ultra-thin body with ultra-thin BOX (UTBB) SOI MOSFETs without a ground plane is studied through measurements and two-dimensional simulations. Two effects causing the output conductance variation with frequency, namely self-heating and source-to-drain coupling through the substrate, are discussed and qualitatively compared. Notwithstanding the use of ultra-thin BOX, which allows for improved heat evacuation from the channel to the Si substrate underneath BOX, a self-heating-related transition clearly appears in the output conductance frequency response. Furthermore, the use of an ultra thin BOX results in an increase of the substrate-related output conductance variation in frequency. As a result, the change in output conductance of UTBB MOSFETs caused by the substrate effect appears to be comparable and even stronger than the change due to self-heating.

38 citations

References
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Journal ArticleDOI
TL;DR: In this paper, the authors analyzed both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compared them to those of normal bulk CMOS process.
Abstract: This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

310 citations


"Floating effective back-gate effect..." refers background in this paper

  • ...minority, and secondly, majority carriers, are no longer able to follow the ac signal [10]....

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Journal ArticleDOI
TL;DR: In this article, a new thermal extraction technique based on an analytically derived expression for the electro-thermal drain conductance in saturation is presented, which can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.
Abstract: Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.

199 citations


"Floating effective back-gate effect..." refers background in this paper

  • ...which was extensively examined [3]–[5]....

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  • ...Moreover, this transition does not show any dependence on the applied biases, on the contrary to what should be observed if this transition was related to the SH [3], [6]....

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Journal ArticleDOI
TL;DR: In this paper, the authors reported a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs, where the AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance and thermal capacitance associated with the SOI device.
Abstract: The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R/sub th/) and thermal capacitance (C/sub th/) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits.

148 citations

Journal ArticleDOI
TL;DR: An original scheme is presented, which allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method.
Abstract: The maturation of low-cost silicon-on-insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs. The extracted model is shown to be valid up to 40 GHz.

138 citations


"Floating effective back-gate effect..." refers methods in this paper

  • ...The small-signal equivalent circuit element values were extracted directly from the measured parameters [8]....

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Journal ArticleDOI
TL;DR: In this article, the physical properties of the surface inversion layer of an MOS capacitance are examined and a second-order two-dimensional model is proposed to explain these anomalies.
Abstract: The physical phenomena associated with the frequency response of the surface inversion layer of an MOS capacitor are examined. It is shown that the equivalent circuit presented by Lehovec and Slobodskoy for an MOS capacitor in the depletion-inversion mode of operation may be simplified when the capacitor is biased in the heavy inversion layer mode. Further it is shown that an additional resistance, to account for generation-recombination in the depletion region, must be included. This new resistance dominates the response for silicon units, which is shown to be as low as I–5o cps at room temperature. Experimentally, there are at least two observations which cannot be explained by the first order one dimensional model on which these equivalent circuits are based. The frequency responses of complementary units, fabricated on almost identical p- and n-type silicon differ by orders of magnitude, it is typically in the range 1–100 cps for n-type units, but may be as high as 10 Mc/s for equivalent p-type units. In addition, pronounced hysteresis in the bias dependence of the capacitance of some p-type units has been observed. A second-order two dimensional model is proposed to explain these anomalies. This model includes an “external” inversion layer, surrounding the gate electrode, produced during the formation of the oxide. The gate inversion layer, in this model, is coupled to the bulk through an additional RC network, representing the external inversion layer, which is in parallel with the equivalent network of the first order model. An approximate analysis of this second order model predicts a frequency response which is in agreement with experiment. The possibility of charge migration on the surface of the oxide, which serves to decouple the gate inversion layer from the external inversion layer, can account for the hysteresis in the capacitance vs. bias characteristics observed in these units.

133 citations


"Floating effective back-gate effect..." refers background in this paper

  • ...The first one introduces the frequency response of the minority carriers by the depletion capacitance and the resistance associated with generation-recombination processes [11], [12]...

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  • ...The equation for is valid only in the strong inversion regime [12], while under other conditions can be neglected....

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