Formal verification of VHDL: the model checker CV
Citations
4 citations
Cites methods from "Formal verification of VHDL: the mo..."
...Similarly to the standard SystemC, authors have defined a sub set of VHDL and defined its semantics in the theorem prover ACL2 [37], or in a certain model checker as CV [38]....
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2 citations
Cites methods from "Formal verification of VHDL: the mo..."
...Finally, we plan to include the heuristics in available verification tools [3, 8] in order to collect further experimental data....
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2 citations
1 citations
Cites background from "Formal verification of VHDL: the mo..."
...In addition to these operational semantics attempts, several others tried to use temporal logics to formalize VHDL [11, 14, 12]....
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Cites methods or result from "Formal verification of VHDL: the mo..."
...in the design process [1] [2] [3], with model-checking being the most used verification procedure....
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...The counterexample as generated by the verification tool is not readable for a VHDL designer and, therefore, it is converted into a VHDL testbench that emulates the undesired behavior, in a similar way to the work by Clarke [2]....
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...emulates the undesired behavior, in a similar way to the work by Clarke [2]....
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References
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"Formal verification of VHDL: the mo..." refers methods in this paper
...Also, we wish to compare the performances of CV other VHDL model checkers[ 11 , 1, 7]. However because of commercial reasons, it will not be an easy task....
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40 citations
"Formal verification of VHDL: the mo..." refers methods in this paper
...Also, we wish to compare the performances of CV other VHDL model checkers[11, 1 , 7]. However because of commercial reasons, it will not be an easy task....
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20 citations
"Formal verification of VHDL: the mo..." refers background in this paper
...The reader interested in technical details is refered to [ DB ], where it is shown precisely how formal verification...
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...in [ DB ]. It reads the intermediate format files produced by th e compiler cva and builds a symbolic, BDD-...
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