Formal verification of VHDL: the model checker CV
30 Jan 1998-pp 95-98
TL;DR: An initial release of the VHDL model checker is completed and it is used to verify complex circuits, including the control logic of a commercial RISC microprocessor.
Abstract: This article describes a prototype formal verification system for a subset of VHDL. The behavior of a VHDL design can be specified with temporal logic formulas and be verified with an algorithm called symbolic model checking. The model checker applies a number of new techniques to handle larger designs, thus allowing for efficient verification of real circuits. We have completed an initial release of the VHDL model checker and have used it to verify complex circuits, including the control logic of a commercial RISC microprocessor.
Citations
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19 Dec 2018
TL;DR: An overview of the most famous formal methods applied to the verification of communication inside NOCs is tried to giva an overview.
Abstract: Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits especially scalability and communication performances. A NOC includes many applications that can execute concurrently. This situation may show some undesirable behaviors such as deadlock, livelock, starvation, etc. On the other hand, the application of formal methods to on-chip communication infrastructures has recieved more attention. Formal analysis of NOC communication will be very advantageous since it allows proving some theorems or interesting qualitative/quantitative properties on the communication behavior where simulation/emulation techniques can fail easily. In this paper we try to giva an overview of the most famous formal methods applied to the verification of communication inside NOCs.
4 citations
Cites methods from "Formal verification of VHDL: the mo..."
...Similarly to the standard SystemC, authors have defined a sub set of VHDL and defined its semantics in the theorem prover ACL2 [37], or in a certain model checker as CV [38]....
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10 Sep 2001
TL;DR: A novel heuristics, called variable weighting, is presented that provides an initial variable ordering for sequential designs and combines extremely, well with existing dynamic variable reordering techniques.
Abstract: Automatic verification of sequential designs has been made possible by the use of efficient representations for propositional logic such as Binary Decision Diagrams (BDDs). However, the efficient use of BDDs is only possible provided a good ordering of the state variables of the design. This paper presents a novel heuristics, called variable weighting, that provides an initial variable ordering for sequential designs. Experiments are provided to illustrate the quality of this algorithm. An important result is that it combines extremely well with existing dynamic variable reordering techniques. In all experiments, the combination of variable weighting and reordering outperforms reordering alone.
2 citations
Cites methods from "Formal verification of VHDL: the mo..."
...Finally, we plan to include the heuristics in available verification tools [3, 8] in order to collect further experimental data....
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01 Sep 2002
TL;DR: To model and verify the correctness of the architecture of the Digital Image Synthesizer (DIS), a system-on-a-chip that synthesizes the characteristic echo signature of a pre- selected target, VHDL was used to create a super class of a 32-Range Bin Modulator.
Abstract: Abstract : The subject of this thesis is to model and verify the correctness of the architecture of the Digital Image Synthesizer (DIS) The DIS, a system-on-a-chip, is especially useful as a counter-targeting repeater. It synthesizes the characteristic echo signature of a pre- selected target. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated. Different software oriented verification approaches were researched and a White-box approach to functional verification was adopted. An algorithm based on the hardware functionality was developed to compare expected and simulated results, Initially, the architecture of one Range Bin Modulator was exported. Modifications to the VHDL source code included modeling of the behavior of the N-FET and P-FET transistors as well as Ground and Vdd (the voltages connected to the drains of the FETs). It also included renaming of entities to comply with VHDL naming conventions. Simulation results were compared to manual calculations and Matlab programs to verify the architecture. The procedure was repeated for the architecture of an Eight-Range Bin Modulator with equally successful results. VHDL was then used to create a super class of a 32-Range Bin Modulator. Test vectors developed in Matlab were used to yet again verify correct functionality.
2 citations
01 Oct 2016
TL;DR: This work investigates a transformation of VHDL descriptions into equivalent formal models that have the same functional simulation behavior as the original V HDL implementation, relying on the BIP component-based modeling language as the underlying formalism.
Abstract: In this work, we investigate a transformation of VHDL descriptions into equivalent formal models. The targeted equivalence is at the level of the functional behavior. That is, we aim at producing formal models that have the same functional simulation behavior as the original VHDL implementation. We rely on the BIP component-based modeling language as the underlying formalism for this transformation. The expected benefits of such a transformation are: enabling the formal verification of hardware designs, allowing for software/hardware system modeling within the same formal framework, and, potentially, accelerating VHDL designs functional simulation by producing distributed BIP models. We show, through a case study, that the transformation is feasible and worth to develop.
1 citations
Cites background from "Formal verification of VHDL: the mo..."
...In addition to these operational semantics attempts, several others tried to use temporal logics to formalize VHDL [11, 14, 12]....
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01 Feb 2016
TL;DR: A synthesizable VHDL design methodology that includes exhaustive verification of properties that was developed in a company environment with the goal of increasing reliability of products and reduce time of verification procedure.
Abstract: In this paper we present a synthesizable VHDL design methodology that includes exhaustive verification of properties. The work was developed in a company environment with the goal of increasing reliability of products and reduce time of verification procedure. In this methodology the properties are represented using VHDL oriented patterns based on the OVL library and applied, with the VHDL code, into a verification environment (based on open source tools) that returns the results. Counterexamples are generated for properties that failed and returned as VHDL testbench, allowing the user to identify the faulty behavior with simulation. The methodology is illustrated with a simple memory controller application.
Cites methods or result from "Formal verification of VHDL: the mo..."
...in the design process [1] [2] [3], with model-checking being the most used verification procedure....
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...The counterexample as generated by the verification tool is not readable for a VHDL designer and, therefore, it is converted into a VHDL testbench that emulates the undesired behavior, in a similar way to the work by Clarke [2]....
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...emulates the undesired behavior, in a similar way to the work by Clarke [2]....
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References
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TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Abstract: In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach.
9,021 citations
TL;DR: It is argued that this technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finite-state concurrent systems.
Abstract: We give an efficient procedure for verifying that a finite-state concurrent system meets a specification expressed in a (propositional, branching-time) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent system. We also show how this approach can be adapted to handle fairness. We argue that our technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finite-state concurrent systems. Experimental results show that state machines with several hundred states can be checked in a matter of seconds.
3,335 citations
13 Jun 1997
TL;DR: This tutorial addresses the following questions: why do formal verification?
Abstract: This tutorial addresses the following questions: why do formal verification? who is doing it today? what are they doing? how are they doing it? what about the future?
78 citations
"Formal verification of VHDL: the mo..." refers methods in this paper
...Also, we wish to compare the performances of CV other VHDL model checkers[ 11 , 1, 7]. However because of commercial reasons, it will not be an easy task....
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01 Jan 1995
TL;DR: An application oriented specification language for assumption/commitment style properties and an abstraction algorithm that generates an intuitive and efficient representation of synchronous circuits that is embedded in the Circuit Verification Environment CVE.
Abstract: This paper describes how model checking has been integrated into an industrial hardware design process. We present an application oriented specification language for assumption/commitment style properties and an abstraction algorithm that generates an intuitive and efficient representation of synchronous circuits. These approaches are embedded in our Circuit Verification Environment CVE. They are demonstrated on two industrial applications.
40 citations
"Formal verification of VHDL: the mo..." refers methods in this paper
...Also, we wish to compare the performances of CV other VHDL model checkers[11, 1 , 7]. However because of commercial reasons, it will not be an easy task....
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02 Oct 1995
TL;DR: Operational semantics for a subset of VHDL in terms of abstract machines is given, which can be used for symbolic model checking and equivalence verification.
Abstract: This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the finiteness of data types, and the absence of quantitative timing informations. The abstract machine of a design unit is built by composition of the abstract machines for its embedded processes and blocks. The kernel process in our model is distributed among the composed machines. One transition of the final abstract machine models a VHDL delta cycle. This model can be used for symbolic model checking and equivalence verification.
20 citations
"Formal verification of VHDL: the mo..." refers background in this paper
...The reader interested in technical details is refered to [ DB ], where it is shown precisely how formal verification...
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...in [ DB ]. It reads the intermediate format files produced by th e compiler cva and builds a symbolic, BDD-...
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