FPGA adders: performance evaluation and optimal design
Shanzhen Xing,W.W.H. Yu +1 more
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The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.Abstract:
Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.read more
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Proceedings ArticleDOI
High-performance carry chains for FPGAs
Scott Hauck,M.M. Hosler,T.W. Fry +2 more
TL;DR: This paper redesigns the standard ripple carry chain to reduce the number of logic levels in each cell, and develops entirely new carry structures based on high performance adders such as Carry Select, Carry Lookahead, and Brent-Kung.
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Deep neural decoders for near term fault-tolerant experiments
TL;DR: In this article, the authors introduce several decoding algorithms complemented by deep neural decoders and apply them to analyze several fault-tolerant error correction protocols such as the surface code as well as Steane and Knill error correction.
Journal ArticleDOI
High-performance carry chains for FPGA's
Scott Hauck,M.M. Hosler,T.W. Fry +2 more
TL;DR: This paper demonstrates how more advanced carry constructs can be embedded into PPGA's, providing significantly higher performance carry computations, and redesigns the standard ripple carry chain to reduce the number of logic levels in each cell.
Proceedings ArticleDOI
Area-Efficient FPGA Implementations of the SHA-3 Finalists
Bernhard Jungk,Jurgen Apfelbeck +1 more
TL;DR: This work focuses on the new SHA-3 competition, started by the National Institute of Standards and Technology (NIST), which searches for a new hash function in response to security concerns regarding the previous hash functions SHA-1 and the SHA-2 family, and provides an evaluation of area-efficient implementations of all finalists.
Proceedings ArticleDOI
Design and characterization of parallel prefix adders using FPGAs
TL;DR: This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse KoggesStone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Add (CSA).
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Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
PRINCIPLES OF CMOS VLSI DESIGN A Systems Perspective Second Edition
Neil Weste,Kamran Eshraghian +1 more
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.
Journal ArticleDOI
A reduced-area scheme for carry-select adders
TL;DR: The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block withBlock- Carry-in 0 to derive a more area-efficient implementation for both the carry-select and parallel-prefix adders.
Book
Computer arithmetic systems: algorithms, architecture and implementation
TL;DR: Topics on floating-point systems redundant signed-digit number systems residue number systems decimal number systems and basic arithmetic basic floating- point operations - implementation elementary functions summary.
Journal ArticleDOI
A Way to Build Efficient Carry-Skip Adders
TL;DR: The optimization problem is reduced to a geometrical problem, solved by means of an algorithm easily implemented on a microcomputer, and an example of the realization of a carry-skip adder is presented.