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Proceedings ArticleDOI

FPGA based image processing unit

01 Oct 2015-pp 1-4
TL;DR: A discussion about implementation of coin counting and simulated result by the help of a language for description of hardware, verilog was done which gives an efficient implementation than normal edge detecting kind of counting coins.
Abstract: In the field of medicine, services based on multimedia and arts Image processing plays a crucial role. The important solution to enhance the quality of systems linked to image processing is hardware based processing of an image. In this a discussion about implementation of coin counting and simulated result by the help of a language for description of hardware, verilog was done. Algorithm for step wise implementation of Brightness manipulation, Operating Threshold and Contrast stretching is implemented which gives an efficient implementation than normal edge detecting kind of counting coins.
References
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Book
01 Jan 2014
TL;DR: Digital image processing 3rd edition free ebooks download, ece 643 digital image processing i chapter 5, gonzfm i xxii 5 1.
Abstract: amazon com digital image processing 3rd edition, digital image processing 3rd edition pdf, digital image processing 3rd edition 9780131687288, een iust ac ir, download digital image processing 3rd edition pdf ebook, digital image processing gonzalez ebay, digital image processing 3rd edition, digital image processing 3rd edition free ebooks download, ece 643 digital image processing i chapter 5, gonzfm i xxii 5 1

1,830 citations

Journal ArticleDOI
01 Aug 2000
TL;DR: A high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user and to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra.
Abstract: Reconfigurable hardware in the form of field programmable gate arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution. However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, the authors present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Their approach is to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations.

114 citations

Journal ArticleDOI
TL;DR: A new reconfigurable parallel architecture oriented to video-rate computer vision applications, structured with a two-dimensional array of FPGA/DSP-based reprogrammable processors Pij, which allows the host to deal with final high-level interpretation tasks.
Abstract: In this article, we present a new reconfigurable parallel architecture oriented to video-rate computer vision applications. This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors Pij. These processors are interconnected by means of a systolic 2D array of FPGA-based video-addressing units which allow video-rate links between any two processors in the net to overcome the associated restrictions in classic crossbar systems such as those which occur with butterfly connections. This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. This proposed open architecture allows the host to deal with final high-level interpretation tasks. The exchange of information between the linked processors Pij of the 2D net lies in the transfer of complete images, pixel by pixel, at video-rate. Therefore, any kind of processor satisfying such a requirement can be integrated. Furthermore, the whole architecture has been designed host-independent.

90 citations

Proceedings ArticleDOI
Knittel1
17 Apr 1996
TL;DR: A small-scale FPGA-coprocessor board for PCI-based systems designed to speed up algorithms from scientific visualization, in particular the visualization of 3D-datasets is presented.
Abstract: We present a small-scale FPGA-coprocessor board for PCI-based systems. It features one XC3195A FPGA (<9 K gate equivalents), three XC4013 devices (each up to 13 K gate equivalents), 2 MByte of Flash Memory, 256 KByte of high-speed SRAM and a 16-bit high-speed multiply-and-accumulate unit. The board was designed to speed up algorithms from scientific visualization, in particular the visualization of 3D-datasets. Such algorithms show a large number of short integer or bit operations, which can efficiently be off-loaded from the CPU to an FPGA-coprocessor. Although being exactly tailored to our application, the accelerator constitutes a versatile platform for other algorithms from image or speech processing. The PCI-bus provides the necessary transfer bandwidth for dataflow-intensive computations.

56 citations

Proceedings ArticleDOI
22 Oct 2007
TL;DR: An image processing system structure based on DSP and FPFA is presented, that is DSP is used as advanced image processing unit and FPGA as logic unit for image sampling and display to meet the real-time requirement.
Abstract: Real-time image processing system is widely used in many field, it is required to have high speed. In order to satisfy the demand, an image processing system structure based on DSP and FPFA is presented, that is DSP is used as advanced image processing unit and FPGA as logic unit for image sampling and display. The hardware configuration and working principle is introduced firstly, and then some key problems which include of image data stored mode, color space conversion and image transmission based on EDMA are described. Finally the program flowchart for developing image processing software is given. The developed system can acquire image, display image and make some image processing operations which include of geometry transform, orthographic transform, operations based on pixels, image compression and color space conversion. The developed system can meet the real-time requirement and has been used in our teaching.

44 citations