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Proceedings ArticleDOI

FPGA based image processing unit usage in coin detection and counting

19 Mar 2015-pp 1-5
TL;DR: Algorithm for step wise implementation of Brightness manipulation, Operating Threshold and Contrast stretching is implemented which gives an efficient implementation than normal edge detecting kind of counting coins.
Abstract: Processing enhancement of a digital Image is really important now a day, as it plays a crucial role in mobile technology, multimedia, medicine and several DSP applications The solution to enhance the quality of systems linked to image processing is hardware based processing of an image by using FPGA'S In this, a discussion about implementation of circle detection and coin counting is done by changing brightness, threshold and contrast of a digital image and simulated result by the help of a language for description of hardware, verilog was done Algorithm for step wise implementation of Brightness manipulation, Operating Threshold and Contrast stretching is implemented which gives an efficient implementation than normal edge detecting kind of counting coins
Citations
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Journal ArticleDOI
TL;DR: In this paper, the authors present a hardware-centric solution, called MeetGo, to address the intrinsic threats to remote computing, such as insider threats committed by adversarial administrators of remote servers who attempt to steal or corrupt users' private data.
Abstract: Remote computing has emerged as a trendy computing model that enables users to process an immense number of computations efficiently on the remote server where the necessary data and high-performance computing power are provisioned. Unfortunately, despite such an advantage, this computing model suffers from insider threats that are committed by adversarial administrators of remote servers who attempt to steal or corrupt users’ private data. These security threats are somewhat innate to remote computing in that there is no means to control administrators’ unlimited data access. In this paper, we present our novel hardware-centric solution, called MeetGo , to address the intrinsic threats to remote computing. MeetGo is a field-programmable gate array (FPGA)-based trusted execution environment (TEE) that aims to operate independently of the host system architecture. To exhibit the ability and effectiveness of MeetGo as a TEE ensuring secure remote computing, we have built two concrete applications: cryptocurrency wallet and GPGPU. MeetGo provides a trust anchor for these applications that enable their users to trade cryptocurrency or to run a GPGPU program server on a remote server while staying safe from threats by insiders. Our experimental results clearly demonstrate that MeetGo incurs only a negligible performance overhead to the applications.

18 citations

Journal ArticleDOI
TL;DR: This assessment development image as a thing to ponder the usage of image acknowledgment development is set itself up as a demonstrating ground to test the suitability of the investigation framework that sees the affirmation of contenders, games affirmation, sports lead judgment, etc.

17 citations

Proceedings ArticleDOI
01 Dec 2017
TL;DR: It is shown that the automatic Thai coin calculation system based on image processing technique can classify and calculate the total value of coins that is useful for the blind persons.
Abstract: In this paper it is introduced an automatic Thai coin calculation system based on image processing technique. It shown that our sytem can classify and calculate the total value of coins that is useful for the blind persons. Image processing used for detection coins in first. After that, SIFT key-points algorithm is used to classification and matching with sound. This system used four types of popular Thai coin in the experimental. We designed our experimental in the different case. In each case, there are different type coin. The least amount of coins is 5 to 40. The accuracy rate shown 99%.

11 citations


Cites background from "FPGA based image processing unit us..."

  • ...Especially they have many coins type and mixed then takes times to identification [5],[6],[8]....

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  • ...So, in counting the coins there are various implement to fix the problem such as coins detection [5], coins recognition [9]-[12]....

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Dissertation
01 May 2017
TL;DR: This thesis outlines the development of an agile, reliable and precise targeting mechanism complete with free space optical communication capabilities for employment in optomechatronic applications and the construction of a FSOC architecture utilizing beam splitter technology.
Abstract: This thesis outlines the development of an agile, reliable and precise targeting mechanism complete with free space optical communication (FSOC) capabilities for employment in optomechatronic applications. To construct the complex mechanism, insight into existing technologies was required. These are inclusive to actuator design, control methodology, programming architecture, object recognition and localization and optical communication. Focusing on each component individually resulted in a variety of novel systems, commencing with the creation of a fast (1.3 ms⁻¹), accurate (micron range) voice coil actuator (VCA). The design, employing a planar, compact composition, with the inclusion of precision position feedback and smooth guidance fulfills size, weight and power (SWaP) characteristics required by many optomechatronic mechanisms. Arranging the VCAs in a parallel nature promoted the use of a parallel orientation manipulator (POM) as the foundation of the targeting structure. Motion control was achieved by adopting a cascade PID-PID control methodology in hardware, resulting in average settling times of 23 ms. In the pursuit of quick and dependable computation, a custom printed circuit board (PCB) containing a field programmable gate array (FPGA), microcontroller and image sensing technology were developed. Subsequently, hardware-based object isolation and parameter identification algorithms were constructed. Furthermore, by integrating these techniques with the dynamic performance of the POM, mathematical equations were generated to allow the targeting of an object in real-time with update rates of 70 ms. Finally, a FSOC architecture utilizing beam splitter technology was constructed and integrated into the targeting device. Thus, producing a system capable of automatically targeting an infrared (IR) light source while simultaneously receiving wireless optical communication achieving ranges beyond 30 feet, at rates of 1 Mbits per second.

6 citations


Cites background from "FPGA based image processing unit us..."

  • ...Supplying an FPGA with pixel information enables many image processing techniques to be accompshied in real-time [73,79,80]....

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  • ...take advantage of brightness and contrast manipulation, as well as thresholding to determine the number of coins in an image [80]....

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Journal ArticleDOI
TL;DR: This paper proposes a highly efficient algorithm designed to run on FPGA whose goal is to monitor the existence of CRAs on the host CPU residing in the same SoC FPGa platform, and develops a unified, lightweight ROP/JOP detection mechanism based on a list of active functions.
Abstract: Field programmable gate arrays (FPGAs) have been increasingly mounted on commodity systems. As a matter of fact, such an emerging adoption of FPGAs in the commodity systems is attributed to their versatility came from the programmable property. Accordingly many industrial and academic attempts have been performed to exploit FPGAs in a variety of applications. In this paper, we note that FPGAs also can be used to protect the host CPU from a nasty security threat, called code reuse attacks (CRAs). Code reuse attack (CRA) is a powerful technique that allows attackers to execute arbitrary code. Control-flow integrity (CFI) has been popularly employed to mitigate CRAs. CFI entails CRA monitoring that checks if a program runs as directed by its control-flow graph. However, as monitoring naturally incurs non-negligible runtime overhead to the host CPU, many studies proposed hardware techniques to lessen the monitoring overhead. To facilitate the immediate deployment of a hardware-based solution, we propose a CRA monitor, called ActiMon , that can be implemented on an SoC FPGA where the host CPU and FPGA are manufactured together in a single platform. However, implementing the CRA monitor operating on FPGA arouses a new challenge that has never been addressed in the previous solutions: the operating clock of FPGA is many times slower than the CPU. By overcoming this speed difference, we ultimately purpose to evince the feasibility of FPGA as a computing device in the field of CRA defense. For this purpose, we have developed a highly efficient algorithm designed to run on FPGA whose goal is to monitor the existence of CRAs on the host CPU residing in the same SoC FPGA platform. Empirical results show that ActiMon runs on our target SoC FPGA platform efficiently enough to catch up to the speed of host code execution and promptly detects two important types of CRAs, JOP (Jump-Oriented Programming) and ROP (Return-Oriented Programming), as soon as they occurred in the host system. We assert that such results are encouraging thanks to our unified, lightweight ROP/JOP detection mechanism based on a list of active functions , and also to additional optimizations to leverage the inherent capabilities of FPGA for parallel computation.

3 citations


Cites background from "FPGA based image processing unit us..."

  • ...Accordingly, many industrial and academic attempts have been performed to exploit FPGAs in a variety of applications—data analytics [7], media processing [8], artificial intelligence [9], network security and monitoring [10], financial [11] and genomics [12]....

    [...]

References
More filters
Journal ArticleDOI
01 Aug 2000
TL;DR: A high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user and to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra.
Abstract: Reconfigurable hardware in the form of field programmable gate arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution. However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, the authors present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Their approach is to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations.

114 citations

Journal ArticleDOI
TL;DR: A new reconfigurable parallel architecture oriented to video-rate computer vision applications, structured with a two-dimensional array of FPGA/DSP-based reprogrammable processors Pij, which allows the host to deal with final high-level interpretation tasks.
Abstract: In this article, we present a new reconfigurable parallel architecture oriented to video-rate computer vision applications. This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors Pij. These processors are interconnected by means of a systolic 2D array of FPGA-based video-addressing units which allow video-rate links between any two processors in the net to overcome the associated restrictions in classic crossbar systems such as those which occur with butterfly connections. This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. This proposed open architecture allows the host to deal with final high-level interpretation tasks. The exchange of information between the linked processors Pij of the 2D net lies in the transfer of complete images, pixel by pixel, at video-rate. Therefore, any kind of processor satisfying such a requirement can be integrated. Furthermore, the whole architecture has been designed host-independent.

90 citations

Journal ArticleDOI
TL;DR: Today, many processors, including digital signal processors, mobile, graphics, and general-purpose central processing units (CPUs) have a multicore design, driven by the demand of higher performance.
Abstract: One of the recent innovations in computer engineering has been the development of multicore processors, which are composed of two or more independent cores in a single physical package. Today, many processors, including digital signal processors (DSPs), mobile, graphics, and general-purpose central processing units (CPUs) have a multicore design, driven by the demand of higher performance. Major CPU vendors have changed strategy away from increasing the raw clock rate to adding on-chip support for multithreading by increases in the number of cores; dual and quad-core processors are now commonplace. Signal and image processing programmers can benefit dramatically from these advances in hardware, by modifying single-threaded code to exploit parallelism to run on multiple cores.

46 citations

Proceedings ArticleDOI
22 Oct 2007
TL;DR: An image processing system structure based on DSP and FPFA is presented, that is DSP is used as advanced image processing unit and FPGA as logic unit for image sampling and display to meet the real-time requirement.
Abstract: Real-time image processing system is widely used in many field, it is required to have high speed. In order to satisfy the demand, an image processing system structure based on DSP and FPFA is presented, that is DSP is used as advanced image processing unit and FPGA as logic unit for image sampling and display. The hardware configuration and working principle is introduced firstly, and then some key problems which include of image data stored mode, color space conversion and image transmission based on EDMA are described. Finally the program flowchart for developing image processing software is given. The developed system can acquire image, display image and make some image processing operations which include of geometry transform, orthographic transform, operations based on pixels, image compression and color space conversion. The developed system can meet the real-time requirement and has been used in our teaching.

44 citations

Proceedings ArticleDOI
05 Jul 2009
TL;DR: This paper used computer visual diagnosis and FPGA-based embedded hardware digital design to classify tiles according to surface and edge defects and used tile images from line camera and the FPGC embedded parallel image processing unit designed with VHDL to reduce computing time.
Abstract: This paper presents one method about automation of tile surface and texture diagnosis. Final stage of tile manufacturing deals with surface and edge defects detection, and is still not an automated part of production. We used computer visual diagnosis and FPGA-based embedded hardware digital design to classify tiles according to surface and edge defects. In order to reduce computing time, we used tile images from line camera and the FPGA embedded parallel image processing unit designed with VHDL.

17 citations