Proceedings ArticleDOI
FPGA-based implementation for steganalysis: a JPEG-compatibility algorithm
E. Gutierrez-Fernandez,Marta Portela-Garcia,Celia Lopez-Ongil,Mario Garcia-Valderas +3 more
- Vol. 8764, pp 876407
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TLDR
A JPEG steganalysis system is implemented in an FPGA in order to speed-up the detection process with respect to software-based implementations and to increase the throughput.Abstract:
Steganalysis is a process to detect hidden data in cover documents, like digital images, videos, audio files, etc. This is the inverse process of steganography, which is the used method to hide secret messages. The widely use of computers and network technologies make digital files very easy-to-use means for storing secret data or transmitting secret messages through the Internet. Depending on the cover medium used to embed the data, there are different steganalysis methods. In case of images, many of the steganalysis and steganographic methods are focused on JPEG image formats, since JPEG is one of the most common formats. One of the main important handicaps of steganalysis methods is the processing speed, since it is usually necessary to process huge amount of data or it can be necessary to process the on-going internet traffic in real-time. In this paper, a JPEG steganalysis system is implemented in an FPGA in order to speed-up the detection process with respect to software-based implementations and to increase the throughput. In particular, the implemented method is the JPEG-compatibility detection algorithm that is based on the fact that when a JPEG image is modified, the resulting image is incompatible with the JPEG compression process.read more
Citations
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Journal ArticleDOI
Novel chaotic random memory indexing steganography on FPGA
TL;DR: Two novel image steganography algorithms are proposed based on generalized chaotic maps based on the generalization technique of logistic maps adding extra degrees of freedom for the design of different chaotic behaviors, thus enhancing the security levels of the proposed algorithms.
Journal ArticleDOI
An analysis of computational models for accelerating the subtractive pixel adjacency model computation
TL;DR: This article presents two computational models for the Subtractive Pixel Adjacency Model (SPAM) which has shown the best detection rates among several assessed steganalysis techniques and the first design proposals to accelerate the SPAM model calculation.
Journal ArticleDOI
A parallel SRM feature extraction algorithm for steganalysis based on GPU architecture
TL;DR: The Spatial Rich Model (SRM) generates powerful steganalysis features, but it has high computational complexity since it requires calculating tens of thousands of convolutions with image noise residuals, so a parallel SRM feature extraction algorithm based on GPU architecture is presented.
Journal ArticleDOI
FPGA image encryption-steganography using a novel chaotic system with line equilibria
TL;DR: In this article , a chaotic system that has line equilibrium points was introduced to enhance the security of image protection, and the whole system was designed and implemented on a field programmable gate array (FPGA).
References
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Proceedings ArticleDOI
Steganalysis based on JPEG compatibility
TL;DR: A new forensic tool that can reliably detect modifications in digital images, such as distortion due to steganography and watermarking, in images that were originally stored in the JPEG format is introduced.
Proceedings ArticleDOI
FPGA hardware of the LSB steganography method
TL;DR: This work presents a hardware design of Least Significant Bit (LSB) steganography technique in a cyclone II FPGA of the Altera family and balances the tradeoffs such as imperceptibility, quality and capacity.
Proceedings ArticleDOI
Error-free computation of 8/spl times/8 2D DCT and IDCT using two-dimensional algebraic integer quantization
TL;DR: A novel error-free (infinite-precision) architecture for the fast implementation of both 8/spl times/8 2D discrete cosine transform and inverse DCT is presented, using a new algebraic integer quantization of a 1D radix-8 DCT that allows the separable computation of a 2D 8/ spl times/ 8 DCT without any intermediate number representation conversions.
Proceedings ArticleDOI
FPGA Hardware Architecture of the Steganographic ConText Technique
TL;DR: A hardware architecture of the ConText steganographic technique in a Cyclone II FPGA of the Altera family and results show a throughput of 61.5 Mbps is presented.
Proceedings ArticleDOI
SteganPEG Steganography + JPEG
TL;DR: Stegan PEG is an application of image steganography that hides files in a JPEG image so that no one can suspect that some sensitive data is being transferred.