FPGA Based Implementation of a Floating Point Multiplier and its Hardware Trojan Models
01 Dec 2019-
TL;DR: Hardware Trojan models are proposed for the mantissa multiplication unit of the floating point multiplier and its FPGA realization with LCD interface for output display to bring out the need for secure hardware design.
Abstract: Floating point multiplication plays a crucial role in computationally intensive applications like digital signal processing. This paper deals with the design of a single precision floating point multiplier and its FPGA realization with LCD interface for output display. To bring out the need for secure hardware design, hardware Trojan models are proposed for the mantissa multiplication unit of the floating point multiplier. Implementation results show that the Trojans produce an average difference of 15%-20% in the product values, an increase of on-chip power by 1.61% and an increase of 0.4% in the number of LUTs. The negligible change in the area and power dissipated establishes the stealthy nature of the proposed Trojans.
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01 Jan 2021
TL;DR: In this paper, a fast Chase decoder has been proposed to improve the speed by replacing the ripple carry adder in the design with a fast adder, and an increase in computation speed of 5% has been achieved.
Abstract: In the field of digital communication, there has always been a requirement for an efficient, low complex, and high-speed error control encoder and decoder. Many such encoders and decoders for different error control codes have been proposed in the literature by researchers. However, developing such CODECs whose performance can be suitable for the requirements of modern communication systems is still an open research problem. In this paper, one such decoder, namely fast Chase decoder proposed in the literature, has been studied. The hardware design of the decoder has been done and verified with results from MATLAB simulations. An attempt has been made to improve the speed by replacing the ripple carry adder in the design with a fast adder. The hardware architecture is implemented in Xilinx XC7A35T platform, and an increase in computation speed of 5% has been achieved.
3 citations
01 Jan 2023
TL;DR: In this article , the authors proposed a Trojan model for a deep neural network (DNN) targeting FPGA platforms, which resulted in a decrease of 26% in the efficiency of the DNN.
Abstract: AbstractNeural networks have started proliferating in various different applications including ones where security can’t be compromised. Training of high performance neural network models involves high hardware requirement and is also very time consuming. This forces users to rely on third party companies for training the neural networks, exposing the trained model to unscrupulous hands and reducing the trustworthiness of the model. It has been reported in literature about mixing of samples of malicious Trojans with training data, the trained network being embedded with hidden functionalities, which can be triggered by specific patterns of the Trojan. Hence it is essential to understand the possibilities of Trojan attacks on local systems. This work is aimed towards proposing a Trojan model for a deep neural network (DNN) targeting FPGA platforms. Insertion of a simple Trojan in the activation module of a neuron resulted in a decrease of 26% in the efficiency of the DNN. This work brings out the need for more efficient defense mechanisms against such Trojans.KeywordsNeural networkHardware trojanVLSIHardware implementationPattern recognition
01 Jan 2023
TL;DR: In this article , the implementation of Hardware Trojans in FPGA based System on Chip (SOC) is carried out and the hardware Trojan is implemented in three different systems and their comparative analysis is carried using the evaluation parameters.
Abstract: In this technologically advancing world, different things are connected together using various integrated systems to collect the data for processing and wise decision-making. These systems are developed using various hardware and software components using different VLSI design and technology with focus on quality of integrated circuits (ICs). There exists security concern during design and development of these ICs in the form of trigger-based hardware that can lead to malicious behavior or destruction of system. This malevolent hardware in ICs is known as Hardware Trojan (HT). Various researchers throughout the world have proposed different methods to detect the Hardware Trojans and to mitigate their effect. There are majorly two perspectives considered for HT detection: one is using layout images examination with physical constraint validation of ICs and the other is during design phase of ICs using hardware description language and assertion checkers to verify and validate the design. In this paper, the implementation of HT in FPGA based System on Chip is carried out. The hardware Trojan is implemented in three different systems and their comparative analysis is carried using the evaluation parameters. These various approaches used to implement are studied in this paper therein labeling the security threats and requirements to deliver the commendation for future research in this field.
References
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TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Abstract: Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.
1,227 citations
"FPGA Based Implementation of a Floa..." refers background in this paper
...Trojans can be classified based on their activation, action and physical characteristics [7]–[9]....
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15 Jul 2014
TL;DR: The threat of hardware Trojan attacks is analyzed; attack models, types, and scenarios are presented; different forms of protection approaches are discussed; and emerging attack modes, defenses, and future research pathways are described.
Abstract: Security of a computer system has been traditionally related to the security of the software or the information being processed. The underlying hardware used for information processing has been considered trusted. The emergence of hardware Trojan attacks violates this root of trust. These attacks, in the form of malicious modifications of electronic hardware at different stages of its life cycle, pose major security concerns in the electronics industry. An adversary can mount such an attack with an objective to cause operational failure or to leak secret information from inside a chip-e.g., the key in a cryptographic chip, during field operation. Global economic trend that encourages increased reliance on untrusted entities in the hardware design and fabrication process is rapidly enhancing the vulnerability to such attacks. In this paper, we analyze the threat of hardware Trojan attacks; present attack models, types, and scenarios; discuss different forms of protection approaches, both proactive and reactive; and describe emerging attack modes, defenses, and future research pathways.
588 citations
"FPGA Based Implementation of a Floa..." refers background in this paper
...Over the years several side-channel and architecture level Trojan detection techniques have been developed [10]....
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TL;DR: A proposed new hardware Trojan taxonomy provides a first step in better understanding existing and potential threats.
Abstract: For reasons of economy, critical systems will inevitably depend on electronics made in untrusted factories. A proposed new hardware Trojan taxonomy provides a first step in better understanding existing and potential threats.
463 citations
21 Sep 2011
TL;DR: This book provides the foundations for understanding hardware security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.
Abstract: This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade. Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems. This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of, and trust in, modern societys microelectronic-supported infrastructures.
407 citations
"FPGA Based Implementation of a Floa..." refers background in this paper
...Hardware Trojans are redundant circuits that cause malicious changes to the functioning of the target circuit [5], [6]....
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20 Nov 2009
TL;DR: The threat posed by hardware Trojans and the methods of deterring them are analyzed, a Trojan taxonomy, models of Trojan operations and a review of the state-of-the-art Trojan prevention and detection techniques are presented.
Abstract: Malicious modification of hardware during design or fabrication has emerged as a major security concern. Such tampering (also referred to as Hardware Trojan) causes an integrated circuit (IC) to have altered functional behavior, potentially with disastrous consequences in safety-critical applications. Conventional design-time verification and post-manufacturing testing cannot be readily extended to detect hardware Trojans due to their stealthy nature, inordinately large number of possible instances and large variety in structure and operating mode. In this paper, we analyze the threat posed by hardware Trojans and the methods of deterring them. We present a Trojan taxonomy, models of Trojan operations and a review of the state-of-the-art Trojan prevention and detection techniques. Next, we discuss the major challenges associated with this security concern and future research needs to address them.
398 citations
"FPGA Based Implementation of a Floa..." refers background in this paper
...Trojans can be classified based on their activation, action and physical characteristics [7]–[9]....
[...]