FPGA Based Novel High Speed DAQ System Design with Error Correction

TLDR: In this article, an efficient high-speed data acquisition (DAQ) design and its implementation on field programmable gate array (FPGA) has been presented, which supports high speed data communication (a#x007E;4.8 Gbps) and achieves multi-bit error correction capabilities.

Abstract: Present state of the art applications in the area of high energy physics experiments (HEP), radar communication, satellite communication and bio medical instrumentation require fault resilient data acquisition (DAQ) system with the data rate in the order of Gbps. In order to keep the high speed DAQsystem functional in such radiation environment where direct intervention of human is not possible, a robust and error free communication system is necessary. In this work we present an efficient DAQ design and its implementation on field programmable gate array (FPGA). The proposed DAQ system supports high speed data communication (a#x007E;4.8 Gbps) and achieves multi-bit error correction capabilities. BCH code (named after Raj Boseand D. K. Ray Chaudhuri) has been used for multi-bit error correction. The design has been implemented on Xilinx Kintex-7board and is tested for board to board communication as well as for board to PC using PCIe (Peripheral Component Interconnect express) interface. To the best of our knowledge, the proposed FPGA based high speed DAQ system utilizing optical link and multi-bit error resiliency can be considered first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, critical path delay, efficiency and bit error rate (BER).