FPGA-Based Novel Speech Enhancement System Using Microphone Activity Detector
01 Jan 2019-pp 117-127
TL;DR: The evaluation of the quality of speech of enhanced signal and its correctness of MAD to detect the single or dual microphone system implies that the proposed hardware can work as a proper embedded component for hardware-based execution for speech enhancement.
Abstract: In this paper, we have proposed field-programmable gate array (FPGA) based design and implementation of a novel speech enhancement system, which can work for a single microphone device as well as that of a dual microphone device providing background noise immunity. We proposed a microphone activity detector (MAD), which detects the presence of single or dual microphone scenario. After detecting the microphones, multiband spectral subtraction technique enhances the speech signal from different background noisy surrounds. We have implemented our proposed design in Spartan 6 LX45 FPGA using Xilinx system generator tools. The evaluation of the quality of speech of enhanced signal and its correctness of MAD to detect the single or dual microphone system implies that our proposed hardware can work as a proper embedded component for hardware-based execution for speech enhancement.
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TL;DR: In this article , a low-power hardware implementation of the log-minimum mean square error (LMMSE) algorithm with statistical-model-based voice activity detection noise estimator is presented.
Abstract: In order to improve the voice quality and decrease the power consumption of the audio electronic products, the noise reduction algorithm and its low-power hardware implementation are studied. Several types of common noise reduction algorithms are analyzed and simulated, and the log-minimum mean square error algorithm with statistical-model-based voice activity detection noise estimator is selected, which can achieve best signal-to-noise ratio improvement of 5.56 dB. The ability of the algorithm to track nonstationary noise is analyzed, and the failure of noise reduction caused by an extreme situation is prevented, and the amount of calculation is reduced by multiplex at the algorithm level. In hardware implementation, look-up tables are used to implement special operations. High-significant-bits search is used to simplify the look-up table to reduce power consumption, and the speed of the search circuit is optimized by parallel design. The exponential integral and exponential operation are combined as one operation with lower precision requirements, leading to lower power consumption. The design presented in this article passed FPGA verification and taped out with a digital hearing aids chip on SMIC 0.13 μm process. The area and the power consumption of the noise reduction module is 0.206 mm2 and 15.3 μW, respectively, which makes the design suitable for low-power audio chip applications.
References
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554 citations
TL;DR: Synthetic microphone signals generated with the image model technique are used to study the effects of room reverberation on the performance of the maximum likelihood estimator of the time delay, in which the estimate is obtained by maximizing the cross correlation between filtered versions of the microphone signals.
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189 citations