FPGA implementation & comparison of current trends in memory scheduler for multimedia application
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"FPGA implementation & comparison of..." refers background in this paper
...Scheduling queue assigns a priority and final data sent to memory are based on different priorities we have considers based on facts observed [8], [4], [1]....
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...Many research papers illustrates pre-charging bank [8], row activate and column accesses [4]....
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...Whereas [4], utilizes non-uniform latencies effectively to increase bus utilization while decreasing execution time of memory....
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29 citations
"FPGA implementation & comparison of..." refers background in this paper
...Scheduling queue assigns a priority and final data sent to memory are based on different priorities we have considers based on facts observed [8], [4], [1]....
[...]
...[1] Bertrand Le Gal, Emmanuel Casseau, and Sylvain Huet...
[...]
...However [1], considers dynamic memory accesses too which are handled in pipelined manner....
[...]
29 citations