FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder

TLDR: This paper deals with the design of an efficient high speed Max-log-MAP decoder that achieves lower latency together with an improved performance in applications including mobile communication and wireless sensor networks.

Abstract: There is a growing demand for high speed error control decoders with improved BER performance in digital communication systems. Turbo codes with its excellent error correcting performance finds wide usage in wireless communication systems. Turbo decoding architecture designs that improve the speed of decoding with acceptable performance is facilitated by efficient and high speed design approaches for the component Max-log-MAP decoders. This paper deals with the design of an efficient high speed Max-log-MAP decoder. High speed operation is achieved by the use of sliding window technique that overcomes the limitation of long decoding delays and improved performance in high SNR regions is obtained by the use of multiple computation units in parallel. This results in an improved architecture that achieves lower latency together with an improved performance. This is significant in applications including mobile communication and wireless sensor networks. The proposed work is implemented in Nexys4 DDR Artix-7 FPGA board and the results are discussed.