FPGA implementation of enhanced key expansion algorithm for Advanced Encryption Standard
01 Nov 2014-pp 409-413
TL;DR: A hardware implementation of the AES-128 encryption and decryption algorithm with the new algorithm of round key expansion is proposed to improve the security against such attacks.
Abstract: Cryptography is a technique related to aspects of information security such as data confidentiality, data integrity and entity authentication In data and telecommunication systems, Security is the most important part for an effective communication, where to increase the security as well as complexity, more randomization in secret keys is necessary to enhance the cryptography algorithms In traditional AES, Even though the round keys have high security, Power analysis attack and Saturation attack are effective to the key expansion algorithm of AES due to the deducible key rounds and it leads to security problems As a result, a new algorithm for generation of round keys is developed for AES On hardware platform, these algorithms are realizing with enormous memory spaces and large execution time An alternative hardware platform scenario is provided by Field programmable gate arrays (FPGAs) due to its reconfiguration nature, marketing speed and low price Accordingly, a hardware implementation of the AES-128 encryption and decryption algorithm with the new algorithm of round key expansion is proposed to improve the security against such attacks This structure will experimentally simulate using Xilinx software with Verilog HDL and hardware implementation on FPGA
Citations
More filters
TL;DR: Two effective algorithms that can be used to solve the main problem facing the AES algorithm and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps are presented.
Abstract: The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the advanced encryption standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.
13Â citations
Additional excerpts
...The Data Encryption Standard (DES) is one of these algorithms [5, 6]....
[...]
TL;DR: The security of encryption techniques depends a great deal on the proper manipulation of keys during the encryption process and improper key handling and use may lead to malicious actors being able to predict the key and consequently endanger the security of the data.
8Â citations
10 Jul 2015
TL;DR: A new pipelined 8-bit architecture for Advanced Encryption Standard (AES) encryption is presented using a more secure key expansion algorithm and high order masking respectively making the overall architecture of AES more secure and less prone to Differential Power Analysis (DPA) attacks.
Abstract: In this paper, we present a new pipelined 8-bit architecture for Advanced Encryption Standard (AES) encryption. The new architecture supports encryption with 128-bit keys with 10 rounds of Byte Substitution, Shift Rows, Mix Columns and Add Round Key operations. We emphasized on optimizing a single round by using an 8-bit architecture instead of 128-bit architecture which resulted into overall optimization and increase in bit security of the system. We have also proposed a new architecture for Key Expansion Unit and S-Box (Substitution Box) using a more secure key expansion algorithm and high order masking respectively, hence making the overall architecture of AES more secure and less prone to Differential Power Analysis (DPA) attacks. The proposed architecture was implemented on Virtex-7 working at a maximum clock frequency of 191.42 MHz with a throughput of 94.24 Mbps and a power consumption of 0.694 W.
8Â citations
01 Dec 2015
TL;DR: A novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length is presented and a new architecture for ByteSubstitution and AddRoundKey operations is proposed, making the proposed architecture less vulnerable to Differential Power Analysis (DPA) and saturation attacks.
Abstract: As network technology advances, information security issues increase the need for developing low-area and low-power high performance real-time processing of cryptographic algorithms. In this paper, we present a novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length. The proposed architecture consists of a single round of ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations through which the data is iterated for ten rounds, which results in substantial reduction in terms of area and power consumption. We have proposed a new architecture for ByteSubstitution and AddRoundKey operations by employing high order masking and a different key expansion algorithm respectively, hence making the proposed architecture less vulnerable to Differential Power Analysis (DPA) and saturation attacks. Moreover, we have also utilized a new architecture for ShiftRows operation for further minimizing the area on chip. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies-Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 200.32 MHz with a throughput of 160.26 Mbps, whereas, with area explore strategy, the proposed architecture utilized 662 slices, 796 LUTs and 0.303 Watt in power.
5Â citations
Cites methods from "FPGA implementation of enhanced key..."
...analysis attacks, hence, we instead employ enhanced key expansion algorithm [26] to generate round keys which is given in the equations (9)-(12):...
[...]
01 Dec 2015
TL;DR: A novel 8-bit pipelined architecture for Advanced Encryption Standard (AES) which ensures high throughput with low area and power consumption and high resistance against Differential Power Analysis and saturation attacks is presented.
Abstract: In accordance with the past trend of technological advancements in hardware implementation of security mechanisms, there is an ongoing decrease in size of cryptographic systems with increase in low power and high throughput constraints. In this paper, we present a novel 8-bit pipelined architecture for Advanced Encryption Standard (AES) which ensures high throughput with low area and power consumption. The proposed architecture supports 10 rounds of encryption, where each round consists ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations. We have employed boolean masking for all AES operations to increase the security of the intermediate data between the operations and the rounds. To increase the resistance against Differential Power Analysis (DPA) and saturation attacks, high order masking and a different key expansion algorithm in ByteSubstitution and for computing round keys in AddRoundKey operation has been employed respectively. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies: Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 175.1 MHz with a throughput of 1400.8 Mbps, whereas, while using the area explore strategy, the proposed architecture utilized 7227 slices, 8709 LUTs and 0.717 Watt in power.
3Â citations
Cites methods from "FPGA implementation of enhanced key..."
...Hence, we employ enhanced key expansion algorithm [17] to generate round keys for the next round, which is given...
[...]
References
More filters
TL;DR: This paper proposes low-cost structure-independent fault detection schemes for the AES encryption and decryption using new formulations for the fault detection of SubBytes and inverse SubBytes using the relation between the input and the output of the S-box and the inverse S-boxes.
Abstract: The Advanced Encryption Standard (AES) has been lately accepted as the symmetric cryptography standard for confidential data transmission. However, the natural and malicious injected faults reduce its reliability and may cause confidential information leakage. In this paper, we study concurrent fault detection schemes for reaching a reliable AES architecture. Specifically, we propose low-cost structure-independent fault detection schemes for the AES encryption and decryption. We have obtained new formulations for the fault detection of SubBytes and inverse SubBytes using the relation between the input and the output of the S-box and the inverse S-box. The proposed schemes are independent of the way the S-box and the inverse S-box are constructed. Therefore, they can be used for both the S-boxes and the inverse S-boxes using lookup tables and those utilizing logic gates based on composite fields. Our simulation results show the error coverage of greater than 99 percent for the proposed schemes. Moreover, the proposed and the previously reported fault detection schemes have been implemented on the most recent Xilinx Virtex FPGAs. Their area and delay overheads have been compared and it is shown that the proposed schemes outperform the previously reported ones.
125Â citations
Proceedings Article•
04 Jun 2009
TL;DR: A method to integrate the AES encrypter and the AES decrypter is proposed, which can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and ( Inv) Mix columns module etc.
Abstract: Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx - Project Navigator, ISE 8.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Xilinx XC3S400 device of Spartan Family is used for hardware evaluation. This paper proposes a method to integrate the AES encrypter and the AES decrypter. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and (Inv) Mix columns module etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.
86Â citations
01 Dec 2011
TL;DR: An FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm that uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase is presented.
Abstract: This paper presents an FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm. The efficient hardware that implements the algorithm is also proposed. The new algorithm (AES-512) uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase. AES-512 will be suitable for applications with high security and throughput requirements and with less chip area constrains such as multimedia and satellite communication systems. An FPGA architectural for AES-512 was developed using VHDL, and synthesized using Virtix-6 and Virtex-7 chips. AES-512 show tremendous throughput increase of 230% when compared with the implementation of the original AES-128.
46Â citations
06 Mar 2010
TL;DR: The principle of AES algorithm and the detailed description and implementation on FPGA, which has less hardware resources and high cost-effective and high security and reliability is introduced.
Abstract: This paper introduces the principle of AES algorithm and the detailed description and implementation on FPGA. This system aims at reduced hardware structure. Compared with the pipeline structure, it has less hardware resources and high cost-effective. And this system has high security and reliability. This AES system can be widely used in the terminal equipments.
34Â citations
TL;DR: This paper describes the process to conduct the CPA attack against AES on SASEBO-GII board and presents a comparison between the Hamming Distance model and the Switching Distance model, in terms of number of power traces needed to recover the correct key using these models.
Abstract: Power analysis attacks are types of side channel attacks that are based on analyzing the power consumption of the cryptographic devices. Correlation power analysis is a powerful and efficient cryptanalytic technique. It exploits the linear relation between the predicted power consumption and the real power consumption of cryptographic devices in order to recover the correct key. The predicted power consumption is determined by using the appropriate consumption model. Until now, only a few models have been proposed and used. In this paper, we describe the process to conduct the CPA attack against AES on SASEBO-GII board. We present a comparison between the Hamming Distance model and the Switching Distance model, in terms of number of power traces needed to recover the correct key using these models. The global successful rate achieves 100% at 11100 power traces. The power traces needed to recover the correct key have been decreased by 12.6% using a CPA attack with Switching Distance model.
22Â citations