FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm
TL;DR: Experimental results suggest that proposed implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm has less latency and hardware utilization as compared to recently proposed implementations.
About: This article is published in Integration.The article was published on 2020-07-01. It has received 13 citations till now. The article focuses on the topics: Twiddle factor & Fast Fourier transform.
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TL;DR: The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtraction to decrease the count of iterations and hardware reduction technique.
Abstract: The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of converge...
5 citations
Cites methods from "FPGA implementation of high-perform..."
...The simulation result shows the CORDIC approach contains lowpower consumption indicates 27.34% and 30.68% and higher frequency indicates 78.30% and 76.57% when likened to the conventional methods (Changela et al., 2020; Franceschi, Camus, Ibrahim, Enz, Valle et al., 2017b)....
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...Also, lower area of the proposed method is 40.49% and 47.84% when compared with conventional CORDIC methods (Changela et al., 2020; Franceschi, Camus, Ibrahim, Enz, Valle et al., 2017a)....
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TL;DR: In this article, the authors proposed a novel coordinate rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant.
4 citations
2 citations
TL;DR: In this article , an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm is proposed, which improves the system's computing speed and reduces the use of registers.
Abstract: Abstract Fast Fourier Transform is widely used in communication and signal processing. I propose an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm. By optimizing the intermediate data processing process and the first stage of pipelining, the architecture improves the system's computing speed and reduces the use of registers. I propose a multiplication scheme based on CORDIC and binary decomposition coding to realize complex number multiplication and constant multiplication and to eliminate the use of a multiplier. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.
1 citations
01 Aug 2020
TL;DR: The proposed architecture is based on two special buffers: the input buffer transforms a given input signal to an upsampled and time-scale compressed form that highly reduces the calculation time of its Fourier transform analysis/synthesis to achieve real-time performance.
Abstract: This paper presents a simple and efficient multirate hardware architecture for real-time signal processing applications. The proposed architecture is based on two special buffers: the input buffer transforms a given input signal to an upsampled and time-scale compressed form that highly reduces the calculation time of its Fourier transform analysis/synthesis to achieve real-time performance. The output buffer transforms back this frame to its original time-scale and sampling frequency. This architecture has been implemented and tested on FPGA (filed programmable gate array) chip using XSG (Xilinx system generator) tool in MATLAB/SIMULINK environment.
1 citations
Cites background from "FPGA implementation of high-perform..."
...Real-time applications require high-throughput, lower latency, and less hardware utilisation [3], [4]....
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References
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TL;DR: Good generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series, applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices.
Abstract: An efficient method for the calculation of the interactions of a 2' factorial ex- periment was introduced by Yates and is widely known by his name. The generaliza- tion to 3' was given by Box et al. (1). Good (2) generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series. In their full generality, Good's methods are applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices, where m is proportional to log N. This results inma procedure requiring a number of operations proportional to N log N rather than N2. These methods are applied here to the calculation of complex Fourier series. They are useful in situations where the number of data points is, or can be chosen to be, a highly composite number. The algorithm is here derived and presented in a rather different form. Attention is given to the choice of N. It is also shown how special advantage can be obtained in the use of a binary computer with N = 2' and how the entire calculation can be performed within the array of N data storage locations used for the given Fourier coefficients. Consider the problem of calculating the complex Fourier series N-1 (1) X(j) = EA(k)-Wjk, j = 0 1, * ,N- 1, k=0
11,795 citations
TL;DR: The trigonometric algorithms used in this computer and the instrumentation of these algorithms are discussed in this paper.
Abstract: The COordinate Rotation DIgital Computer(CORDIC) is a special-purpose digital computer for real-time airborne computation. In this computer, a unique computing technique is employed which is especially suitable for solving the trigonometric relationships involved in plane coordinate rotation and conversion from rectangular to polar coordinates. CORDIC is an entire-transfer computer; it contains a special serial arithmetic unit consisting of three shift registers, three adder-subtractors, and special interconnections. By use of a prescribed sequence of conditional additions or subtractions, the CORDIC arithmetic unit can be controlled to solve either set of the following equations: Y' = K(Y cos? + X sin?) X' = K(X cos? - Y sin?), or R = K?X2 + Y2 ? = tan-1 Y/X, where K is an invariable constant. This special arithmetic unit is also suitable for other computations such as multiplication, division, and the conversion between binary and mixed radix number systems. However, only the trigonometric algorithms used in this computer and the instrumentation of these algorithms are discussed in this paper.
2,639 citations
Book•
09 Sep 1999TL;DR: An indispensable resource for instruction, professional development, and research, Computer Arithmetic: Algorithms and Hardware Designs, Second Edition combines broad coverage of the underlying theories of computer arithmetic with numerous examples of practical designs, worked-out examples, and a large collection of meaningful problems.
Abstract: Ideal for graduate and senior undergraduate courses in computer arithmetic and advanced digital design, Computer Arithmetic: Algorithms and Hardware Designs, Second Edition, provides a balanced, comprehensive treatment of computer arithmetic. It covers topics in arithmetic unit design and circuit implementation that complement the architectural and algorithmic speedup techniques used in high-performance computer architecture and parallel processing. Using a unified and consistent framework, the text begins with number representation and proceeds through basic arithmetic operations, floating-point arithmetic, and function evaluation methods. Later chapters cover broad design and implementation topics-including techniques for high-throughput, low-power, fault-tolerant, and reconfigurable arithmetic. An appendix provides a historical view of the field and speculates on its future.An indispensable resource for instruction, professional development, and research, Computer Arithmetic: Algorithms and Hardware Designs, Second Edition, combines broad coverage of the underlying theories of computer arithmetic with numerous examples of practical designs, worked-out examples, and a large collection of meaningful problems. This second edition includes a new chapter on reconfigurable arithmetic, in order to address the fact that arithmetic functions are increasingly being implemented on field-programmable gate arrays (FPGAs) and FPGA-like configurable devices. Updated and thoroughly revised, the book offers new and expanded coverage of saturating adders and multipliers, truncated multipliers, fused multiply-add units, overlapped quotient digit selection, bipartite and multipartite tables, reversible logic, dot notation, modular arithmetic, Montgomery modular reduction, division by constants, IEEE floating-point standard formats, and interval arithmetic.Features:* Divided into 28 lecture-size chapters * Emphasizes both the underlying theories of computer arithmetic and actual hardware designs * Carefully links computer arithmetic to other subfields of computer engineering * Includes 717 end-of-chapter problems ranging in complexity from simple exercises to mini-projects * Incorporates many examples of practical designs * Uses consistent standardized notation throughout * Instructor's manual includes solutions to text problems * An author-maintained website http://www.ece.ucsb.edu/~parhami/text_comp_arit.htm contains instructor resources, including complete lecture slides
1,517 citations
TL;DR: A brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications is presented.
Abstract: Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.
521 citations
TL;DR: The CORDIC iteration is applied to several Fourier transform algorithms and a new, especially attractive FFT computer architecture is presented as an example of the utility of this technique.
Abstract: The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware configurations are examined for cost, speed, and complexity tradeoffs. A new, especially attractive FFT computer architecture is presented as an example of the utility of this technique. Compensated and modified CORDIC algorithms are also developed.
304 citations