Proceedings ArticleDOI
FPGA implementation of high speed multiplier using higher order compressors
Ramalatha Marimuthu,S. Balamurugan,Bala Krishna Tirumala,Partha Sharathi Mallick +3 more
- pp 210-212
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TLDR
This proposed paper is using higher order compressors to execute the multiplication operation, as these compressors have less delay, low power consumption but also occupies slightly larger area and this helps in incrementing of execution speed of whole multiplier.Abstract:
In general applications such as image processing signal processing and many similar applications find most of the work is done through multipliers to execute complex instructions. We generally use low order compressors for this multiplication operations. In this proposed paper, we are using higher order compressors to execute the multiplication operation. As these compressors have less delay, low power consumption but also occupies slightly larger area and this helps in incrementing of execution speed of whole multiplier.read more
Citations
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Journal ArticleDOI
Design of Efficient Signed Multiplier Using Compressors for FFT Architecture
R Marimuthu,P. S. Mallick +1 more
TL;DR: This paper presents design of signed multiplier using various compressors with two and one signed bit for signed multipliers, which provides low power dissipation and high-speed than a conventional signed multiplier.
Proceedings ArticleDOI
Low-power and high-performance 5:2 compressors
TL;DR: Two novel 5:2 compressors are presented, developed to limit the carry propagation to one compressor, thereby reducing the overall propagation delay and compared with the best architectures presented in the literature in terms of power, delay and area.
Proceedings ArticleDOI
High speed multipliers using nested higher order compressors
TL;DR: The proposed paper puts to usage, higher order compressors for the same purpose, which results in reduced delay and improves efficiency greatly.
Journal Article
Energy Efficient Implementation of Modified 4:2 Compressor in High Speed Multipliers
TL;DR: The observation is that the usage of compressor makes the process more energy efficient and faster as compared to the traditional methods.
Journal Article
A Unique Low-Power Implementation of 4-2 Compressor in High Speed Multiplier
TL;DR: The usage of compressor makes the process more energy efficient and faster as compared to the traditional methods, and the delay and power-delay product (PDP) is proven to have minimum delay and PDP.
References
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Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal ArticleDOI
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Proceedings ArticleDOI
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
TL;DR: Novel architectures and designs of high speed, low power 3-2, 4-2 and 5-2 compressors capable of operating at ultra-low voltages are presented and are shown to perform better.
Proceedings ArticleDOI
Low-power 4-2 and 5-2 compressors
TL;DR: This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units, which are building blocks for binary multipliers.
Journal ArticleDOI
High performance low power array multiplier using temporal tiling
TL;DR: Based on simulation studies, a temporally tiled array multiplier achieves 50% and 35% improvements in delay and power dissipation compared to a conventional array multiplier.