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Proceedings ArticleDOI

FPGA implementation of high speed multiplier using higher order compressors

TL;DR: This proposed paper is using higher order compressors to execute the multiplication operation, as these compressors have less delay, low power consumption but also occupies slightly larger area and this helps in incrementing of execution speed of whole multiplier.
Abstract: In general applications such as image processing signal processing and many similar applications find most of the work is done through multipliers to execute complex instructions. We generally use low order compressors for this multiplication operations. In this proposed paper, we are using higher order compressors to execute the multiplication operation. As these compressors have less delay, low power consumption but also occupies slightly larger area and this helps in incrementing of execution speed of whole multiplier.
Citations
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Journal ArticleDOI
TL;DR: This paper presents design of signed multiplier using various compressors with two and one signed bit for signed multipliers, which provides low power dissipation and high-speed than a conventional signed multiplier.
Abstract: This paper presents design of signed multiplier using various compressors. We have designed 4-3 and 5-3 compressors with two and one signed bit for signed multipliers. This signed multiplier provides low power dissipation and high-speed than a conventional signed multiplier. In addition, we have designed Radix -2 four-point FFT structure using the proposed signed multipliers. We have used 5-3 multicolumn compressor to combine adders and subtractors in the fourpoint FFT structure. It gives better performance in terms of speed and power. Additionally, pipeline concept has been incorporated in the four-point butterfly structure, which further decrease delay and power. This design was implemented using Cadence RTL compiler with TSMC 90nm technology.

5 citations


Cites methods from "FPGA implementation of high speed m..."

  • ...Several techniques have been used to obtain low power like bypassing techniques and various types of new compressors are introduced in the partial product reduction stage [5,6,7,8,9,10,11,12,13,14,15,16,17,18]....

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Proceedings ArticleDOI
20 May 2014
TL;DR: Two novel 5:2 compressors are presented, developed to limit the carry propagation to one compressor, thereby reducing the overall propagation delay and compared with the best architectures presented in the literature in terms of power, delay and area.
Abstract: Compressors play a significant role in overall performance of multipliers and hence in efficiency of arithmetic circuits. To further improvement of multipliers higher order compressors have been considered. In this paper, two novel 5:2 compressors are presented. The proposed architectures lay emphasis on the idea of making the carry-out signal C out2 independent of C in1 . Therefore, we have developed our designs to limit the carry propagation to one compressor, thereby reducing the overall propagation delay. In addition, in some compressor designs, one or more full-adder (FA)-equivalent building block(s) can be found. Using a particular CMOS FA in our design, we have introduced a more optimized architecture. The proposed architectures are compared with the best architectures presented in the literature in terms of power, delay and area. Simulations have been conducted by HSPICE software at 90nm technology. Simulation results of the proposed architectures show up to 30% improvement in Power-Delay Product (PDP) for the supply voltage of 1V and ambient temperature of 25°C.

4 citations


Cites background from "FPGA implementation of high speed m..."

  • ...Many papers have made use of novel high-order compressors for further improvement of multipliers’ performance [6, 7]....

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Proceedings ArticleDOI
16 Oct 2014
TL;DR: The proposed paper puts to usage, higher order compressors for the same purpose, which results in reduced delay and improves efficiency greatly.
Abstract: Lot of applications today employ multipliers to do many simple and complex jobs, from mathematical calculations to signal processing. But we only employ lower order compressors for this operation. This gives us lot of delay. The proposed paper puts to usage, higher order compressors for the same purpose. This results in reduced delay and improves efficiency greatly.

1 citations

Journal Article
TL;DR: The observation is that the usage of compressor makes the process more energy efficient and faster as compared to the traditional methods.
Abstract: This paper sheds light upon the usage of 4:2 compressor in 4x4 and 8x8 Wallace tree multipliers. Usage of compressors in multipliers improves the efficiency and reduces the processing time. A modified 4:2 compressor design is discussed and its performance is compared with the conventional 4:2 compressor. The modified 4:2 compressor uses a combination of XOR-XNOR and MUX* gates. The concept of these compressors for improving the performance of the multiplier is done on transistor level. The performance of these different designs is compared and the observation is that the usage of compressor makes the process more energy efficient and faster as compared to the traditional methods. In case of 4 bit multipliers usage of modified 4:2 compressors reduced the delay by 38.2% and propagation delay product by 34.7%. Similarly usage of 4:2 compressors in 8 bit multipliers reduced the delay by 42% and propagation delay product by 47%.

Cites background from "FPGA implementation of high speed m..."

  • ...It has become the most indispensible operation of the modern processing equipment [1,2,3,4,5,6,7,8,9]....

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  • ...The multiplication process can be divided into three stages namely the generation of partial product, reduction of the partial product and the final addition [1,2,3,4,5,6,7,8,15,16,17,18]....

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  • ...This usage of compressor has shown a commendable improvement in the multiplication process on the whole [1,3,4,5,6,7,8,9,19,20,21]....

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Journal Article
TL;DR: The usage of compressor makes the process more energy efficient and faster as compared to the traditional methods, and the delay and power-delay product (PDP) is proven to have minimum delay and PDP.
Abstract: On using these Compressors in the multiplier, the number of interconnections gets reduced, which further produces quick results, along with consuming lesser power. The concept of these compressors for improving the performance of the multiplier is done on transistor level. The performance of these different designs is compared and the observation is that the usage of compressor makes the process more energy efficient and faster as compared to the traditional methods. The delay and power-delay product (PDP) is compared with earlier Wallace and Dadda Multipliers, implemented with 4-2 Compressors and without compressors, and is proven to have minimum delay and PDP.
References
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Journal ArticleDOI
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Abstract: It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, ?sec, and quotients in 3 ?sec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.

1,750 citations


"FPGA implementation of high speed m..." refers background in this paper

  • ...210 978-1-4673-2758-9/12/$31.00 ©2012 IEEE processing signal processing and many similar applications find most of the work is done through multipliers to execute complex instructions....

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Journal ArticleDOI
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Abstract: This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.

349 citations


"FPGA implementation of high speed m..." refers background in this paper

  • ...Generally, multiplication has three stages of execution, first is the generation of partial products followed by reduction of those and ends with computation of final product....

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Proceedings ArticleDOI
06 Jan 2007
TL;DR: Novel architectures and designs of high speed, low power 3-2, 4-2 and 5-2 compressors capable of operating at ultra-low voltages are presented and are shown to perform better.
Abstract: The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and designs of high speed, low power 3-2, 4-2 and 5-2 compressors capable of operating at ultra-low voltages are presented. The power consumption, delay and area of these new compressor architectures are compared with existing and recently proposed compressor architectures and are shown to perform better. The proposed architecture lays emphasis on the use of multiplexers in arithmetic circuits that result in high speed and efficient design. Also in all existing implementations of XOR gate and multiplexers, both output and its complement are available but current designs of compressors do not use these outputs efficiently. In the proposed architecture these outputs are efficiently utilized to improve the performance of compressors. The combination of low power, low transistor count and lesser delay makes the new compressors a viable option for efficient design

152 citations

Proceedings ArticleDOI
01 Jan 2001
TL;DR: This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units, which are building blocks for binary multipliers.
Abstract: This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units. These compressors are building blocks for binary multipliers. Various circuit architectures for 4-2 compressors are compared with respect to their delay and power consumption. The different circuits are simulated using HSPICE. A new circuit for a 5-2 compressor is then presented which is 12% faster and consumes 37% less power.

116 citations


Additional excerpts

  • ...…)) (4) where, a I0 I1 ; b I0 I1; c I2 I3 I4 ; d ((I2 I3) | (I2 I4) | (I3 I4)); e I5 I6 I7 f ((I5 I6) | (I5 I7) | (I6 I7)) The above equations are implemented to develop a 8-4 compressor which has 8 inputs and gives 4 outputs this helps in very rapid execution of the instructions....

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Journal ArticleDOI
TL;DR: Based on simulation studies, a temporally tiled array multiplier achieves 50% and 35% improvements in delay and power dissipation compared to a conventional array multiplier.
Abstract: Digital multipliers are a major source power dissipation in digital signal processors. Array architecture is a popular technique to implement these multipliers due to its regular compact structure. High power dissipation in these structures is mainly due to the switching of a large number of gates during multiplication. In addition, much power is also dissipated due to a large number of spurious transitions on internal nodes. Timing analysis of a full adder, which is a basic building block in array multipliers, has resulted in a different array connection pattern that reduces power dissipation due to the spurious transition activity. Furthermore, this connection pattern also improves the multiplier throughput. This array pattern is based on creating a compact tiled structure, wherein the shape of a tile represents the delay through that tile. That is, a compact structure created using these tiles is nothing but a structure with high throughput. Such a temporal tiling technique can also be applied to other digital circuits. Based on our simulation studies, a temporally tiled array multiplier achieves 50% and 35% improvements in delay and power dissipation compared to a conventional array multiplier. Improvement in delay can be traded for power using voltage reduction techniques.

68 citations


Additional excerpts

  • ...…)) (4) where, a I0 I1 ; b I0 I1; c I2 I3 I4 ; d ((I2 I3) | (I2 I4) | (I3 I4)); e I5 I6 I7 f ((I5 I6) | (I5 I7) | (I6 I7)) The above equations are implemented to develop a 8-4 compressor which has 8 inputs and gives 4 outputs this helps in very rapid execution of the instructions....

    [...]