FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics
01 Jan 2013-
TL;DR: An efficient implementation of an IEEE 754 single precision floating point multiplier using vedic mathematics so that the area and power constraints of thefloating point multiplier can be reduced efficiently.
Abstract: In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier using vedic mathematics .The purpose of using vedic mathematics is due to increase in the number of partial products in normal multiplication process ,with using vedic mathematics partial products can be reduced so that the area and power constraints of the floating point multiplier can be reduced efficiently. Keywords-floatingpoint; multiplication, FPGA, Nikhilamsutra, Radix selection unit, Vedic mathematics.
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01 Nov 1997
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Abstract: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful. You have remained in right site to begin getting this info. acquire the computer organization and design the hardware software interface 4th fourth edition by patterson hennessy join that we manage to pay for here and check out the link.
832 citations
TL;DR: This work proposes designing of high speed floating point multipliers using Vedic Mathematics, which has a regular structure therefore can be easily layout in a Silicon chip.
18 citations
09 Jul 2015
TL;DR: A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm is used to implement unsigned binary multiplier for mantissa multiplication which gives a better implementation in terms of delay and power.
Abstract: Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.
17 citations
01 Jan 2015
TL;DR: A IEEE-754 single precision floating point multiplier which handles over flow, under flow and rounding is proposed which will have a great impact on improving the speed and reduce the area required on Spartan 6 FPGA.
Abstract: Multiplication of floating point numbers found extensive use in DSP applications involving huge range. The critical part in floating point multiplication is the multiplication of mantissas which uses 24∗24 bit integer multiplier for single precision floating point numbers. The speed of the system can be enhanced by improving the speed of multiplication. In this paper a 24 bit Vedic multiplier has been proposed using 3∗3 Vedic multiplier as its basic block. This paper proposes a IEEE-754 single precision floating point multiplier which handles over flow, under flow and rounding. The proposed and conventional floating point multipliers based on Vedic mathematics are coded in Verilog, Synthesized and simulated in ISE Simulator. It is implemented on iWave Systems Unified Learning Kit (ULK), which is Spartan6 family xc6slx25t-2fgg484 FPGA. Maximum combinational path delay and number of slices required on FPGA are compared for proposed and conventional multipliers. The results clearly indicate that proposed method have a great impact on improving the speed and reduce the area required on Spartan 6 FPGA.
14 citations
Cites background from "FPGA Implementation of Low-Area Flo..."
...Floating point numbers represent real numbers in binary format....
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01 May 2016
TL;DR: A floating point multiplier which manages overflow, underflow and rounding, based on Vedic Urdhva - Tiryagbhyam mathematics is proposed which is proposed to implement faster multipliers involving limited area and consuming reduced power.
Abstract: Floating point number can co-occurrently develop a prominent range of numbers and a high level of precision. Multiplication of floating point numbers found extensive use in wider range of technological and commercial calculations. It is needed to implement faster multipliers involving limited area and consuming reduced power. An IEEE-754 format established multiplier applying Vedic Urdhva — Tiryagbhyam mathematics will be cultivated to cover both single precision and double precision format floating point numbers in the paper. This paper proposes a floating point multiplier which manages overflow, underflow and rounding. The proposed and conventional floating point multipliers based on Vedic mathematics would be coded in Verilog, Synthesized and Simulated using ISE Simulator. Xilinx Virtex VI FPGA will be used for Hardware realization and Verification. It is proposed to compare resource utilization and timing performance of the proposed multiplier with that of existing as of now.
12 citations
Cites methods from "FPGA Implementation of Low-Area Flo..."
...Xilinx Virtex VI platform FPGA usage for the implementation of Floating Point numbers rather than microprocessor based configurations will be the leading choice due to high speed operation, parallel processing, re-programmability....
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Book•
01 Jan 1993
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
Abstract: What's New in the Third Edition, Revised Printing The same great book gets better! This revised printing features all of the original content along with these additional features:. Appendix A (Assemblers, Linkers, and the SPIM Simulator) has been moved from the CD-ROM into the printed book. Corrections and bug fixesThird Edition featuresNew pedagogical features.Understanding Program Performance -Analyzes key performance issues from the programmer's perspective .Check Yourself Questions -Helps students assess their understanding of key points of a section .Computers In the Real World -Illustrates the diversity of applications of computing technology beyond traditional desktop and servers .For More Practice -Provides students with additional problems they can tackle .In More Depth -Presents new information and challenging exercises for the advanced student New reference features .Highlighted glossary terms and definitions appear on the book page, as bold-faced entries in the index, and as a separate and searchable reference on the CD. .A complete index of the material in the book and on the CD appears in the printed index and the CD includes a fully searchable version of the same index. .Historical Perspectives and Further Readings have been updated and expanded to include the history of software R&D. .CD-Library provides materials collected from the web which directly support the text. In addition to thoroughly updating every aspect of the text to reflect the most current computing technology, the third edition .Uses standard 32-bit MIPS 32 as the primary teaching ISA. .Presents the assembler-to-HLL translations in both C and Java. .Highlights the latest developments in architecture in Real Stuff sections: -Intel IA-32 -Power PC 604 -Google's PC cluster -Pentium P4 -SPEC CPU2000 benchmark suite for processors -SPEC Web99 benchmark for web servers -EEMBC benchmark for embedded systems -AMD Opteron memory hierarchy -AMD vs. 1A-64 New support for distinct course goals Many of the adopters who have used our book throughout its two editions are refining their courses with a greater hardware or software focus. We have provided new material to support these course goals: New material to support a Hardware Focus .Using logic design conventions .Designing with hardware description languages .Advanced pipelining .Designing with FPGAs .HDL simulators and tutorials .Xilinx CAD tools New material to support a Software Focus .How compilers work .How to optimize compilers .How to implement object oriented languages .MIPS simulator and tutorial .History sections on programming languages, compilers, operating systems and databases On the CD.NEW: Search function to search for content on both the CD-ROM and the printed text.CD-Bars: Full length sections that are introduced in the book and presented on the CD .CD-Appendixes: Appendices B-D .CD-Library: Materials collected from the web which directly support the text .CD-Exercises: For More Practice provides exercises and solutions for self-study.In More Depth presents new information and challenging exercises for the advanced or curious student .Glossary: Terms that are defined in the text are collected in this searchable reference .Further Reading: References are organized by the chapter they support .Software: HDL simulators, MIPS simulators, and FPGA design tools .Tutorials: SPIM, Verilog, and VHDL .Additional Support: Processor Models, Labs, Homeworks, Index covering the book and CD contents Instructor Support Instructor support provided on textbooks.elsevier.com:.Solutions to all the exercises .Figures from the book in a number of formats .Lecture slides prepared by the authors and other instructors .Lecture notes
1,521 citations
01 Nov 1997
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Abstract: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful. You have remained in right site to begin getting this info. acquire the computer organization and design the hardware software interface 4th fourth edition by patterson hennessy join that we manage to pay for here and check out the link.
832 citations
17 Apr 1996
TL;DR: This work has explored FPGA implementations of addition and multiplication for IEEE single precision floating-point numbers, and prototypes have been implemented on Altera FLEX8000s, and peak rates of 7 MFlops for 32-bit addition and 2.3 M flop multiplication have been obtained.
Abstract: Floating point operations are hard to implement on FPGAs because of the complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, we have explored FPGA implementations of addition and multiplication for IEEE single precision floating-point numbers. Customizations were performed where this was possible in order to save chip area, or get the most out of our prototype board. The implementations tradeoff area and speed for accuracy. The adder is a bit-parallel adder, and the multiplier is a digit-serial multiplier. Prototypes have been implemented on Altera FLEX8000s, and peak rates of 7 MFlops for 32-bit addition and 2.3 MFlops for 32-bit multiplication have been obtained.
128 citations
TL;DR: An assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.
Abstract: We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic. >
93 citations
03 Nov 2002
TL;DR: A group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA are presented, taking advantage of special features of the technology to produce optimised components.
Abstract: The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of /spl sim/100 MHz single-precision components. Non-pipelined reference designs are included for future comparison purposes.
74 citations