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Proceedings ArticleDOI: 10.1109/GET.2015.7453796

FPGA implementation of universal asynchronous transmitter and receiver

01 Nov 2015-pp 1-3
Abstract: The proposed work in this paper describes the implementation of universal asynchronous transmitter and receiver, that is UART. The UART is a type of a serial communication protocol which serves the purpose of full duplex communication over a serial link. The UART here in is described by hardware description language that is Verilog HDL. The Verilog HDL code has been simulated in the ModelSim 10.1d and implemented on Altera DE1 board.

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Topics: Universal asynchronous receiver/transmitter (70%), Serial port (61%), ModelSim (60%) ...read more
Citations
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Proceedings ArticleDOI: 10.1109/ICCMC.2019.8819628
Durga Prasad V Rao1, Aishwarya Raja1, R Karthikeyan1, K Vijay Pal  +2 moreInstitutions (1)
01 Mar 2019-
Abstract: MIL-STD 1553B serial bus is used in spacecraft for information exchange between subsystems. The three main elements of this 1553B bus are Bus Controller, Remote Terminal and Bus Monitor. This paper describes about the design and implementation of bus controller for a test system that focuses on the Test and Evaluation (T&E) of Onboard Bus interface (1553B) system. The design and implementation is carried out using Quartus 13.1.4 Web Edition on custom made Cyclone III FPGA board.

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Topics: Control bus (77%), Serial communication (57%)

Open accessJournal Article
Abstract: In the due course of time, due to rising development cost and density of VLSI chips and turnaround time, it turns out to be critical to have a verification methodology, which empowers first pass chips to be entirely functional and error free. Universal Verification Methodology (UVM) facilitates the communication through TLM interface. On account of its excellent architecture of AMBA and simplicity of AHB bus it has been widely used in several SOC designs. This paper is focused on developing a Verification IP (VIP) for Multi-master AMBA AHB protocol using System Verilog based UVM environment. AMBA-AHB provides a high bandwidth system bus which can perform multiple operations in parallel. This project also depicts how Verification IP is used to verify the AHB Components-Arbiter, Slave, Master and Decoder. With the UVM based VIP, it was able to achieve MDV (Metric Driven Verification) and assertion based verification which has drastically minimized the time spent on verification of a design.The Verification IP is developed using Cadence tool Ncsim and can be reused to verify any AHB based system design.

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Topics: Universal Verification Methodology (64%), Verilog (54%), System bus (52%)
References
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Proceedings ArticleDOI: 10.1109/ISA.2011.5873448
Yi-yuan Fang1, Xue-jun Chen1Institutions (1)
28 May 2011-
Abstract: UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. It's significant for the design of SOC. The simulation results with Quartus II are completely consistent with the UART protocol.

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Topics: Universal asynchronous receiver/transmitter (66%), Serial port (65%), VHDL (54%) ...read more

81 Citations


Proceedings ArticleDOI: 10.1109/ICIEA.2007.4318890
Shouqian Yu1, Lili Yi1, Weihai Chen2, Zhaojin Wen1Institutions (2)
23 May 2007-
Abstract: To meet modern complex control systems communication demands, the paper presents a multi-channel UART controller based on FIFO (first in first out) technique and FPGA (field programmable gate array). The paper presents design method of asynchronous FIFO and structure of the controller. This controller is designed with FIFO circuit block and UART (universal asynchronous receiver transmitter) circuit block within FPGA to implement communication in modern complex control systems quickly and effectively. Form the communication sequence diagrams, it is easily to know that this controller can be used to implement communication when master equipment and slaver equipment are set at different Baud Rate. It also can be used to reduce synchronization error between sub-systems in a system with several sub-systems. The controller is reconfigurable and scalable.

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26 Citations


Proceedings ArticleDOI: 10.1109/IS3C.2012.10
04 Jun 2012-
Abstract: The proposed paper describes the universal asynchronous receiver/transmitter i.e. UART which is the kind of serial communication protocol which allows the full duplex communication in serial link. This paper presents the hardware implementation of a high speed and efficient UART using FPGA. The UART consists of three main components namely transmitter, receiver and baud rate generator which is nothing but the frequency divider. This has been simulated on ModelSim SE 10.0a and has been implemented by using Verilog description language which has been synthesized on FPGA kits such as Virtex4 and Spartan3.

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Topics: Universal asynchronous receiver/transmitter (66%), Serial port (63%), ModelSim (56%) ...read more

22 Citations


Proceedings ArticleDOI: 10.1109/ICIT.2005.1600623
Xiaoyin Shao1, Dong Sun1Institutions (1)
14 Dec 2005-
Abstract: In this paper, a new motion control IC is developed and implemented in field programmable gate array (FPGA). The core of this design is a flexible motion control engine, designed with Verilog HDL language, and implementation on an industry standard FPGA provided by Xilinx. The new FPGA based motion control IC has functions of closed current loop control, closed position/velocity loop control, incremental encoder logic, PWM modulation, fault/brake logic, velocity estimator, host communication module, UART module and delta-sigma analog to digital converter. The hardware system executes quickly in dedicated parallel hardware without timing overhead penalty of a serial processor. The update rates of the current control loop and position/velocity control loop are 120 kHz and 20 kHz, respectively. Experimental results are given to verify the effectiveness of the proposed FPGA based motion control IC

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Topics: Motion control (60%), Field-programmable gate array (57%), Control system (56%) ...read more

18 Citations


Proceedings ArticleDOI: 10.1109/ICCCI.2014.6921826
16 Oct 2014-
Abstract: Core dynamic power is independent of output load capacitance. IO power and static power is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if we scale down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits that transmit/receive data between parallel and serial forms and vice versa. Design state of our design is high because no black box found. Bit width is high because 57.6% of primitives in RTL net list represent 1-bit logic. Here, IO power consumption is 17,226mW on 10,000pF output load which significantly reduce to 47mW on 5pF output load. Along with reduction in IOs power, we also observed 24.5% reduction in static power consumption from 1322mW on 10,000pF output load to 1004mW on 5pF output load. In our implementation on FPGA, we take Virtex-6 family, XC6VLX75T device, FF484 package, −1 speed grade, XST synthesis tool, ISim simulator, and Verilog as preferred HDL language.

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14 Citations


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