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FPGA implementation of variable precision Euclid’s GCD algorithm

TL;DR: This paper implements a fast GCD coprocessor based on Euclid's method with variable precisions (32-bit to 1024-bit) and shows that the design area is scalable and can be easily increased or embedded with many other design applications.
Abstract: Introduction: Euclid's algorithm is well-known for its efficiency and simple iterative to compute the greatest common divisor (GCD) of two non-negative integers. It contributes to almost all public key cryptographic algorithms over a finite field of arithmetic. This, in turn, has led to increased research in this domain, particularly with the aim of improving the performance throughput for many GCD-based applications. Methodology: In this paper, we implement a fast GCD coprocessor based on Euclid's method with variable precisions (32-bit to 1024-bit). The proposed implementation was benchmarked using seven field programmable gate arrays (FPGA) chip families (i.e., one Altera chip and six Xilinx chips) and reported on four cost complexity factors: the maximum frequency, the total delay values, the hardware utilization and the total FPGA thermal power dissipation. Results: The results demonstrated that the XC7VH290T-2-HCG1155 and XC7K70T-2-FBG676 devices recorded the best maximum frequencies of 243.934 MHz down to 39.94 MHz for 32-bits with 1024-bit precisions, respectively. Additionally, it was found that the implementation with different precisions has utilized minimal resources of the target device, i.e., a maximum of 2% and 4% of device registers and look-up tables (LUT’s). Conclusions: These results imply that the design area is scalable and can be easily increased or embedded with many other design applications. Finally, comparisons with previous designs/implementations illustrate that the proposed coprocessor implementation is faster than many reported state-of-the-art solutions. This paper is an extended version of our conference paper [1].
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Posted Content
TL;DR: In this article, the authors investigate a method that computes the GCD of two 32-bit numbers based on Euclidean algorithm which targets six different Xilinx chips and the complexity of this method is achieved by utilizing Sum of Absolute Difference (SAD) block which is based on a fast carry-out generation function.
Abstract: Euclids algorithm is widely used in calculating of GCD (Greatest Common Divisor) of two positive numbers. There are various fields where this division is used such as channel coding, cryptography, and error correction codes. This makes the GCD a fundamental algorithm in number theory, so a number of methods have been discovered to efficiently compute it. The main contribution of this paper is to investigate a method that computes the GCD of two 32-bit numbers based on Euclidean algorithm which targets six different Xilinx chips. The complexity of this method that we call Optimized_GCDSAD is achieved by utilizing Sum of Absolute Difference (SAD) block which is based on a fast carry-out generation function. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency), area delay product (ADP) and space (slice number) complexity. The VHDL codes of these architectures have been implemented and synthesized through ISE 14.7. A detailed comparative analysis indicates that the proposed Optimized_GCDSAD method based on SAD block outperforms previously known results.
References
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Book
15 Jan 2002
TL;DR: A full chapter on error correcting codes introduces the basic elements of coding theory and provides a flexible organization, as each chapter is modular and can be covered in any order.
Abstract: From the Publisher: This book assumes a minimal background in programming and a level of math sophistication equivalent to a course in linear algebra. It provides a flexible organization, as each chapter is modular and can be covered in any order. Using Mathematica, Maple, and MATLAB, computer examples included in an Appendix explain how to do computation and demonstrate important concepts. A full chapter on error correcting codes introduces the basic elements of coding theory. Other topics covered: Classical cryptosystems, basic number theory, the data encryption standard, AES: Rijndael, the RSA algorithm, discrete logarithms, digital signatures, e-commerce and digital cash, secret sharing schemes, games, zero knowledge techniques, key establishment protocols, information theory, elliptic curves, error correcting codes, quantum cryptography. For professionals in cryptography and network security.

497 citations

Book
01 Jan 2004

265 citations


"FPGA implementation of variable pre..." refers background in this paper

  • ...Millions of logic gates and tens of thousands of flip-flops can co-exist in a single design technology tool via field programmable gate arrays (FPGAs) [2]....

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Book ChapterDOI
01 Jan 2004
TL;DR: In this article, the authors considered a mixed system in which all operands and results are serial, although it is possible to have some inputs and outputs are serial and others parallel.
Abstract: In the previous chapters we described algorithms and implementations for arithmetic modules that have the inputs applied all at once (in parallel) and deliver same digit lines. The system is usually clocked so that one digit is applied/deliveredper clock cycle. This serial alternative is the topic of this chapter. We consider thea mixed system in which in which all operands and results are serial, although it is possible to have some inputs and outputs are serial and others parallel. The methods to design these mixed systems can be devised from those for paralleland serial systems.

145 citations

Book
12 May 2009

42 citations


"FPGA implementation of variable pre..." refers background or methods in this paper

  • ...Number theory [8, 10] was largely separated from other fields of mathematics since it is topically related to elementary arithmetic....

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  • ...The “Euclidean algorithm” [8] and “Sieve of Eratosthenes” [10] are both recent candidates to implement....

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  • ...It also arrives at the solution faster within a single cycle [10]....

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  • ...There are many algorithms that can be used to compute the GCD [8, 10]....

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Journal ArticleDOI
TL;DR: The proposed design comprises six levels: random two prime numbers, parallel multiplication of the prime numbers and their decremented values, get encryption key, get decryption key, encryption and decryption levels, and Interleaved Algorithm was particularly chosen as an efficient solution to speed up the modular multiplication.

17 citations


"FPGA implementation of variable pre..." refers background or methods in this paper

  • ...Shamir, and Adleman) cryptosystem is a good example of a GCD application that uses cryptoalgorithms [5], and the trusted platform module (TPM) uses RSA as a building block [6]....

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  • ...The efficient design-based FPGA technology has recently emerged in many fields and applications, such as high-performance computing, networking, security and cryptography, as in [5, 6]; fault tolerance applications, as in [7]; and many other regular and irregular applications....

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