FPGA implementation of vedic floating point multiplier
23 Apr 2015-pp 1-4
TL;DR: An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers.
Abstract: Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.
Citations
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06 Apr 2016
TL;DR: This paper presents the highly efficient 64 bit Vedic multiplier for the mantissa calculation using rule or sutra of Vedic mathematics called Urdhva Tiryakbhyam Sutra which deals with vertically and crosswise multiplication.
Abstract: As floating point architecture is very hot topic for researchers so challenges are always there to design the efficient Floating point architecture. Out of other operations, Floating point multiplication is the most commonly used operation and it requires the multiplication of the mantissa of Floating point numbers. This paper presents the highly efficient 64 bit multiplier for the mantissa calculation using rule or sutra of Vedic mathematics called Urdhva Tiryakbhyam Sutra which deals with vertically and crosswise multiplication. Using this sutra in the computation algorithm of DSP processors, can enhance the efficiency and at the same time can reduce the complexity, area, power consumption and delay. Starting from the design of 2 bit Vedic multiplier we went up to design 64 bit Vedic multiplier as presented in this paper. Vedic multiplier is coded in Verilog HDL and targeted to three different families of FPGA Spartan6, Virtex5 and Virtex6 in Xilinx 13.1 ISE software. Result is compared with the Karatsuba, Vedic-Karatsuba and Optimized Vedic multiplier and found 33% reduction in delay.
19 citations
Cites methods from "FPGA implementation of vedic floati..."
...They had also shown that based on the device utilization and performance comparison, Vedic multiplier outperforms Karatsuba multiplier both for 32 bit and 64 bit format [4]....
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TL;DR: The results of simulation indicate that the latency of the proposed novel binary multiplier systems (8-bit, 16-bit and 24-bit) with significantly shorter than existing implementations.
Abstract: Arithmetic Logic Units (ALUs) are very important components of the processor, which performs various arithmetic and logical operations such as multiplication, division, addition, subtraction, cubing, squaring, etc. Of these all operations, multiplication is most elementary and most frequently used operation in the ALUs. The operation of multiplication also forms the basis of many other complex arithmetic operations such as cubing, squaring, convolution, etc. This paper presents the modified novel multi-precision binary multiplier architecture to achieve a reduced latency/delay and area/hardware utilization along with existing implementations of binary multiplication. This system will function as second stage of the of a novel multi-precision binary multiplier system. The system was implemented using Xilinx 14.2 ISE and simulated with ISIM which was available from Xilinx 14.2 ISE. The results of simulation indicate that the latency of the proposed novel binary multiplier systems (8-bit, 16-bit and 24-bit) with significantly shorter than existing implementations.
16 citations
TL;DR: This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary representation in Urdhva Tiryagbhyam (UT) sutra, the first ever effort towards extension of Vedic algorithms to the signed numbers.
Abstract: This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary (RB) representation in Urdhva Tiryagbhyam (UT) sutra. This is the first ever effort towards extension of Vedic algorithms to the signed numbers. The proposed multiplier architecture solves the carry propagation issue in UT sutra, as carry free addition is possible in RB representation. The proposed design is coded in VHDL and synthesised in Xilinx ISE 14.4 of various FPGA devices. The proposed SVM architecture has better speed performances as compared with various state-of-the-art conventional as well as Vedic architectures.
13 citations
TL;DR: A fast signed binary multiplication structure based on Vedic Nikhilam algorithm that achieves speed improvement over prior design and leads to significant gains in speed by converting a large operand multiplication to small operands multiplication, along with addition.
Abstract: Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand multiplication to small operand multiplication, along with addition. The proposed design is synthesised with Xilinx ISE 14.4 software and realised using different field programmable gate array devices. The efficiency of the proposed design depends on combinational delay, area and power. Moreover, the new multiplier architecture achieves speed improvement over prior design.
7 citations
01 Nov 2018
TL;DR: The proposed high speed multiplier using Urdhva-Tiryakbhyam (UT) technique with modified Carry Save Adders (CSA) is implemented and outperform existing multipliers used for FP Division in terms of speed and accuracy.
Abstract: Most of the Digital operations in computing systems performed by using Floating-Point (FP) arithmetic. FP multiplication is widely used arithmetic operation compared to addition, subtraction and division operations. Multipliers performed using Vedic technique shows higher speed of operation with better precision but it occupies slightly more area compared to conventional multipliers. In this paper, we implemented 24-bit Vedic multiplier using Urdhva-Tiryakbhyam (UT) technique with modified Carry Save Adders (CSA). The proposed high speed multiplier is used for calculating Mantissa part (24-bit) in single precision FP Division. This method outperform existing multipliers used for FP Division in terms of speed and accuracy. All the design parameters are evaluated using VIVADO synthesis tool and results are verified by simulation. The design was coded in Verilog HDL and is implemented in NEXYS 4 DDR FPGA kit.
5 citations
Cites methods from "FPGA implementation of vedic floati..."
...TABLE II provides the device utilization summary and latency for Wallace, Urdhva Tiryakbhyam [14] and Proposed UT multipliers....
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...Logic Utilization Wallace UT Multiplier [14] Proposed UT Multiplier...
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References
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15 Jul 2009
TL;DR: The efficiency of Urdhva Triyagbhyam-Vedic method for multiplication is proved which strikes a difference in the actual process of multiplication itself, which enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm.
Abstract: The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of ALU depends greatly on the multiplier. In algorithmic and structural levels, numerous multiplication techniques have been developed to enhance the efficiency of the multiplier which concentrates in reducing the partial products and the methods of their addition but the principle behind multiplication remains the same in all cases. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. Though there are many sutras employed to handle different sets of numeric, exploring each one gives new results. Our work has proved the efficiency of Urdhva Triyagbhyam-Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. This sutra is to be used to build a high speed power efficient multiplier in the coprocessor.
123 citations
"FPGA implementation of vedic floati..." refers background in this paper
...This Vedic coprocessor will be more efficient than its conventional counterpart [11]....
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...A comparison of time delays for various types of multipliers for different key lengths is presented in [11]....
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TL;DR: It is concluded that the new rounding algorithm is the fastest rounding algorithm, provided that an injection can be added in during the reduction of the partial products into a carry-save encoded digit string.
Abstract: A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner (1995) and of Quach et al. (1991). For each rounding algorithm, a logical description and a block diagram is given, the correctness is proven, and the latency is analyzed. We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision format, the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al. and 16 logic levels in the algorithm of Yu and Zyner.
89 citations
02 Jun 2011
TL;DR: A high speed complex multiplier design using Vedic mathematics is presented in this paper, where partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB.
Abstract: Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/sub-tractor unit is adopted from ancient Indian mathematics “Vedas”. On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting (16, 16)×(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. We achieved almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel adder and DA based architectures.
81 citations
"FPGA implementation of vedic floati..." refers background in this paper
...A performance comparison of array multiplier and vedic multiplier has been presented in [12]....
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14 Apr 1999
TL;DR: It is concluded that the new rounding algorithm is the fastest rounding algorithm, provided that an injection can be added in during the reduction of the partial products into a carry-save encoded digit string.
Abstract: A novel IEEE compliant floating point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of R. Yu and G. Zyner (1995) and of N. Quach et al. (1991). For each rounding algorithm, a logical description and a block diagram is given and the latency is analyzed. We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al., and 16 logic levels in the algorithm of Yu and Zyner.
67 citations
"FPGA implementation of vedic floati..." refers background in this paper
...About 37 % of the floating point instructions in benchmark applications constitute floating point multiplications [1]....
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06 Mar 2014
TL;DR: Compressor based Vedic Multipliers based on Vedic mathematics show considerable improvements in speed and area efficiency over the conventional ones.
Abstract: Multipliers are the key block in high speed arithmetic logic units, multiplier and accumulate units, digital signal processing units etc. With the increasing constraints on delay, more and more emphasis is being laid on design of faster multiplications. To enhance speed many modifications over the standard modified booth algorithm, Wallace tree methods for multiplier design have been made and several new techniques are being worked upon. Amongst these Vedic multipliers based on Vedic mathematics are presently under focus due to these being one of the fastest and low power multiplier. There are sixteen sutras in Vedic multiplication in which “Urdhva Tiryakbhyam” has been noticed to be the most efficient one in terms of speed. A large number of high speed Vedic multipliers have been proposed with Urdhva Tiryakbhyam sutra. Few of them are presented in this paper giving an insight into their methodology, merits and demerits. Compressor based Vedic Multipliers show considerable improvements in speed and area efficiency over the conventional ones.
51 citations
"FPGA implementation of vedic floati..." refers background in this paper
...Vedic mathematics put forth by Swami Bharati Krishna Tirtha as an embodiment of 16 sutras and 13 sub sutras provide algorithms for various arithmetic operations [2], [3]....
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