Proceedings ArticleDOI
Front end device for content networking
Jeremy Buboltz,Taskin Kocak +1 more
- pp 1456-1461
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TLDR
This paper proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm, implemented in VHDL, synthesized, and laid out on an Altera FPGA.Abstract:
The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This paper proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA.read more
Citations
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Journal ArticleDOI
A pipelined processor architecture for regular expression string matching
TL;DR: This special purpose processor is a parallel and pipelined architecture which can deal with the regular expression semantics and can achieve 200-400 times speedup over traditional CPU implementations and up to 7.9Gbps in processing throughput.
Journal Article
An extensible, system-on-programmable-chip, content-aware Internet firewall
John W. Lockwood,C.E. Neely,Christopher K. Zuver,James Moscola,Sarang Dharmapurikar,David Lim +5 more
TL;DR: An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates as mentioned in this paper, using layered protocol wrappers to parse the content of Internet data.
Book ChapterDOI
Implementation of Compressed Brute-Force Pattern Search Algorithm Using VHDL
TL;DR: This paper implemented search process to perform compressed pattern matching in binary Huffman encoded texts by applying Brute-Force Search algorithm and evaluating pattern matching processes in terms of clock cycle.
References
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Journal ArticleDOI
Efficient string matching: an aid to bibliographic search
TL;DR: A simple, efficient algorithm to locate all occurrences of any of a finite number of keywords in a string of text that has been used to improve the speed of a library bibliographic search program by a factor of 5 to 10.
Journal ArticleDOI
A fast string searching algorithm
TL;DR: The algorithm has the unusual property that, in most cases, not all of the first i .” in another string, are inspected.
Journal ArticleDOI
Locality-aware request distribution in cluster-based network servers
Vivek S. Pai,Mohit Aron,Gaurov Banga,Michael Svendsen,Peter Druschel,Willy Zwaenepoel,Erich M. Nahum +6 more
TL;DR: A simple, practical strategy for locality-aware request distribution (LARD), in which the front-end distributes incoming requests in a manner that achieves high locality in the back-ends' main memory caches as well as load balancing.
Proceedings ArticleDOI
Assisting network intrusion detection with reconfigurable hardware
TL;DR: A module generator that extracts strings from the Snort NIDS rule-set, generates a regular expression that matches all extracted strings, synthesizes a FPGA-based string matching circuit, and generates an EDIF netlist that can be processed by Xilinx software to create an FPGAs bitstream is developed.
Proceedings ArticleDOI
Scalable pattern matching for high speed networks
TL;DR: The efficiency of the technique enables a current-generation FPGA device to support pattern-matching at network rates from 1 Gbps to 100 Gbps and beyond and offers flexible trade-offs between character capacity, throughput, and data bus width and rate.