scispace - formally typeset
Search or ask a question
Proceedings ArticleDOI

Fuzzy fairness controller for NVMe SSDs

TL;DR: This work proposes a fuzzy logic-based fairness control mechanism that characterizes the degree of flow intensity of a workload and assigns priorities to the workloads and observes that the proposed mechanism improves the fairness, weighted speedup, and harmonic speedup of SSD by 29.84, 11.24, and 24.90% on average over state of the art.
Abstract: Modern NVMe SSDs are widely deployed in diverse domains due to characteristics like high performance, robustness, and energy efficiency. It has been observed that the impact of interference among the concurrently running workloads on their overall response time differs significantly in these devices, which leads to unfairness. Workload intensity is a dominant factor influencing the interference. Prior works use a threshold value to characterize a workload as high-intensity or low-intensity; this type of characterization has drawbacks due to lack of information about the degree of low- or high-intensity. A data cache in an SSD controller - usually based on DRAMs - plays a crucial role in improving device throughput and lifetime. However, the degree of parallelism is limited at this level compared to the SSD back-end consisting of several channels, chips, and planes. Therefore, the impact of interference can be more pronounced at the data cache level. No prior work has addressed the fairness issue at the data cache level to the best of our knowledge. In this work, we address this issue by proposing a fuzzy logic-based fairness control mechanism. A fuzzy fairness controller characterizes the degree of flow intensity (i.e., the rate at which requests are generated) of a workload and assigns priorities to the workloads. We implement the proposed mechanism in the MQSim framework and observe that our technique improves the fairness, weighted speedup, and harmonic speedup of SSD by 29.84%, 11.24%, and 24.90% on average over state of the art, respectively. The peak gains in fairness, weighted speedup, and harmonic speedup are 2.02x, 29.44%, and 56.30%, respectively.
Citations
More filters
Journal ArticleDOI
TL;DR: In this article , the authors present a methodological survey of cache management policies for these three types of internal caches in SSDs and derive a set of guidelines for a future cache designer, and enumerates a number of future research directions for designing an optimal SSD internal cache management policy.

5 citations

Journal ArticleDOI
TL;DR: In this article, the authors present a methodological survey of cache management policies for these three types of internal caches in SSDs and derive a set of guidelines for a future cache designer, and enumerates a number of future research directions for designing an optimal SSD internal cache management policy.

5 citations

Journal ArticleDOI
TL;DR: A DRAM-based Over-Provisioning (OP) cache management mechanism, named Justitia, to reduce data cache contention and improve fairness for modern SSDs is proposed.
Abstract: Modern NVMe SSDs have been widely deployed in multi-tenant cloud computing environments or multi-programming systems. When multiple applications concurrently access one SSD hardware, unfairness within the shared SSD will slow down the application significantly and lead to a violation of service level objectives. However, traditional data cache management within SSDs mainly focuses on improving cache hit ratio, which causes data cache contention and sacrifices fairness among multiple applications. In this paper, we propose a DRAM-based Over-Provisioning (OP) cache management mechanism, named Justitia, to reduce data cache contention and improve fairness for modern SSDs. Justitia consists of two stages including Static-OP stage and Dynamic-OP stage. Through the novel OP mechanism in the two stages, Justitia reduces the max slowdown by 4.5x on average. At the same time, Justitia increases fairness by 20.6x and buffer hit ratio by 19.6% averagely, compared with the traditional shared mechanism.

2 citations

Journal ArticleDOI
TL;DR: The proposed write-related and read-related DRAM allocation strategy inside solid-state drives (SSDs) can reduce more reads/writes in NAND flash memory than other methods to improve the response time.
Abstract: Although NAND flash memory has the advantages of small size, low-power consumption, shock resistance, and fast access speed, NAND flash memory still faces the problems of “out-of-place updates,” “garbage collection,” and “unbalanced execution time” due to its hardware limitations. Usually, a flash translation layer (FTL) can maintain the mapping cache (in limited DRAM space) to store the frequently accessed address mapping for “out-of-place updates” and maintain the read/write buffer (in limited DRAM space) to store the frequently accessed data for “garbage collection” and “unbalanced execution time”. In this article, we will propose a write-related and read-related DRAM allocation strategy inside solid-state drives (SSDs). The design idea behind the write-related DRAM allocation method is to calculate the suitable DRAM allocation for the write buffer and the write mapping cache by building a statistical model with a minimum expected value of writes for NAND flash memory. To further reduce reads in NAND flash memory, the design idea behind the read-related DRAM allocation method is to adopt a cost-benefit policy to reallocate the proper DRAM space from the write buffer and the write mapping cache to the read buffer and the read mapping cache, respectively. According to the experimental results, we can demonstrate that the proposed write-related and read-related DRAM allocation strategy can reduce more reads/writes in NAND flash memory than other methods to improve the response time.
Journal ArticleDOI
TL;DR: Wang et al. as discussed by the authors proposed a conflict-free (CF) lane to eliminate conflicts by dividing I/O requests into conflictfree PU queues based on physical addresses, which correspond to the PU resources within the NVMe SSDs.
References
More filters
Book
01 Jan 2001
TL;DR: This chapter discusses Type-2 Fuzzy Sets, a New Direction for FLSs, and Relations and Compositions on different Product Spaces on Different Product Spaces, as well as operations on and Properties of Type-1 Non-Singleton Type- 2 FuzzY Sets.
Abstract: (NOTE: Each chapter concludes with Exercises.) I: PRELIMINARIES. 1. Introduction. Rule-Based FLSs. A New Direction for FLSs. New Concepts and Their Historical Background. Fundamental Design Requirement. The Flow of Uncertainties. Existing Literature on Type-2 Fuzzy Sets. Coverage. Applicability Outside of Rule-Based FLSs. Computation. Supplementary Material: Short Primers on Fuzzy Sets and Fuzzy Logic. Primer on Fuzzy Sets. Primer on FL. Remarks. 2. Sources of Uncertainty. Uncertainties in a FLS. Words Mean Different Things to Different People. 3. Membership Functions and Uncertainty. Introduction. Type-1 Membership Functions. Type-2 Membership Functions. Returning to Linguistic Labels. Multivariable Membership Functions. Computation. 4. Case Studies. Introduction. Forecasting of Time-Series. Knowledge Mining Using Surveys. II: TYPE-1 FUZZY LOGIC SYSTEMS. 5. Singleton Type-1 Fuzzy Logic Systems: No Uncertainties. Introduction. Rules. Fuzzy Inference Engine. Fuzzification and Its Effect on Inference. Defuzzification. Possibilities. Fuzzy Basis Functions. FLSs Are Universal Approximators. Designing FLSs. Case Study: Forecasting of Time-Series. Case Study: Knowledge Mining Using Surveys. A Final Remark. Computation. 6. Non-Singleton Type-1 Fuzzy Logic Systems. Introduction. Fuzzification and Its Effect on Inference. Possibilities. FBFs. Non-Singleton FLSs Are Universal Approximators. Designing Non-Singleton FLSs. Case Study: Forecasting of Time-Series. A Final Remark. Computation. III: TYPE-2 FUZZY SETS. 7. Operations on and Properties of Type-2 Fuzzy Sets. Introduction. Extension Principle. Operations on General Type-2 Fuzzy Sets. Operations on Interval Type-2 Fuzzy Sets. Summary of Operations. Properties of Type-2 Fuzzy Sets. Computation. 8. Type-2 Relations and Compositions. Introduction. Relations in General. Relations and Compositions on the Same Product Space. Relations and Compositions on Different Product Spaces. Composition of a Set with a Relation. Cartesian Product of Fuzzy Sets. Implications. 9. Centroid of a Type-2 Fuzzy Set: Type-Reduction. Introduction. General Results for the Centroid. Generalized Centroid for Interval Type-2 Fuzzy Sets. Centroid of an Interval Type-2 Fuzzy Set. Type-Reduction: General Results. Type-Reduction: Interval Sets. Concluding Remark. Computation. IV: TYPE-2 FUZZY LOGIC SYSTEMS. 10. Singleton Type-2 Fuzzy Logic Systems. Introduction. Rules. Fuzzy Inference Engine. Fuzzification and Its Effect on Inference. Type-Reduction. Defuzzification. Possibilities. FBFs: The Lack Thereof. Interval Type-2 FLSs. Designing Interval Singleton Type-2 FLSs. Case Study: Forecasting of Time-Series. Case Study: Knowledge Mining Using Surveys. Computation. 11. Type-1 Non-Singleton Type-2 Fuzzy Logic Systems. Introduction. Fuzzification and Its Effect on Inference. Interval Type-1 Non-Singleton Type-2 FLSs. Designing Interval Type-1 Non-Singleton Type-2 FLSs. Case Study: Forecasting of Time-Series. Final Remark. Computation. 12. Type-2 Non-Singleton Type-2 Fuzzy Logic Systems. Introduction. Fuzzification and Its Effect on Inference. Interval Type-2 Non-Singleton Type-2 FLSs. Designing Interval Type-2 Non-Singleton Type-2 FLSs. Case Study: Forecasting of Time-Series. Computation. 13. TSK Fuzzy Logic Systems. Introduction. Type-1 TSK FLSs. Type-2 TSK FLSs. Example: Forecasting of Compressed Video Traffic. Final Remark. Computation. 14. Epilogue. Introduction. Type-2 Versus Type-1 FLSs. Appropriate Applications for a Type-2 FLS. Rule-Based Classification of Video Traffic. Equalization of Time-Varying Non-linear Digital Communication Channels. Overcoming CCI and ISI for Digital Communication Channels. Connection Admission Control for ATM Networks. Potential Application Areas for a Type-2 FLS. A. Join, Meet, and Negation Operations For Non-Interval Type-2 Fuzzy Sets. Introduction. Join Under Minimum or Product t-Norms. Meet Under Minimum t-Norm. Meet Under Product t-Norm. Negation. Computation. B. Properties of Type-1 and Type-2 Fuzzy Sets. Introduction. Type-1 Fuzzy Sets. Type-2 Fuzzy Sets. C. Computation. Type-1 FLSs. General Type-2 FLSs. Interval Type-2 FLSs. References. Index.

2,555 citations

Book
01 Sep 1997
TL;DR: Drawing on their extensive experience working with industry on implementations, Kevin Passino and Stephen Yurkovich have written an excellent hands-on introduction for professionals and educators interested in learning or teaching fuzzy control.
Abstract: From the Publisher: Fuzzy control is emerging as a practical alternative to conventional methods of solving challenging control problems. Written by two authors who have been involved in creating theoretical foundations for the field and who have helped assess the value of this new technology relative to conventional approaches, Fuzzy Control is filled with a wealth of examples and case studies on design and implementation. Computer code and MATLAB files can be downloaded for solving the book's examples and problems and can be easily modified to implement the reader's own fuzzy controllers or estimators. Drawing on their extensive experience working with industry on implementations, Kevin Passino and Stephen Yurkovich have written an excellent hands-on introduction for professionals and educators interested in learning or teaching fuzzy control.

2,207 citations

Proceedings Article
Hyun-Chul Kim1, Seongjun Ahn1
26 Feb 2008
TL;DR: A new write buffer management scheme called Block Padding Least Recently Used is proposed, which significantly improves the random write performance of flash storage and shows about 44% enhanced performance for the workload of MS Office 2003 installation.
Abstract: Flash memory has become the most important storage media in mobile devices, and is beginning to replace hard disks in desktop systems However, its relatively poor random write performance may cause problems in the desktop environment, which has much more complicated requirements than mobile devices While a RAM buffer has been quite successful in hard disks to mask the low efficiency of random writes, managing such a buffer to fully exploit the characteristics of flash storage has still not been resolved In this paper, we propose a new write buffer management scheme called Block Padding Least Recently Used, which significantly improves the random write performance of flash storage We evaluate the scheme using trace-driven simulations and experiments with a prototype implementation It shows about 44% enhanced performance for the workload of MS Office 2003 installation

477 citations


"Fuzzy fairness controller for NVMe ..." refers background in this paper

  • ...Data cache management in SSD: A number of research-works on data cache management [11, 17, 37, 38] focus on cache space management to improve SSD throughput and lifetime....

    [...]

Proceedings ArticleDOI
01 Jan 2001
TL;DR: This paper investigates fetch policies that find a balance between fairness and throughput and discusses techniques to use a set of pipeline system variables for achieving balanced throughput and fairness.
Abstract: Simultaneous Multithreading (SMT) is an execution model that executes multiple threads in parallel within a single processor pipeline. Usually, an SMT processor uses shared instruction queues to collect instructions from the different threads. Hence, an SMT processor’s performance depends on how the instruction fetch unit fills these instruction queues every cycle. In the recent past, many schemes have been proposed for fetching instructions into the SMT pipeline. These schemes focussed on increasing the throughput by using the number of instructions and the number of low confidence branch predictions currently in the pipeline, to decide which threads to fetch from. The goal of this paper is to investigate fetch policies that find a balance between fairness and throughput. We present metrics to quantify fairness. We then discuss techniques to use a set of pipeline system variables for achieving balanced throughput and fairness. Finally, we evaluate several fetch policies. Our evaluation confirms that many of our fetch policies provide a good balance between throughput and fairness.

308 citations


"Fuzzy fairness controller for NVMe ..." refers background in this paper

  • ...Harmonic speedup (Equation-5) provides a good measure of performance and fairness [23]....

    [...]

Proceedings ArticleDOI
03 Dec 2011
TL;DR: In this paper, the authors present an alternative approach to reduce inter-application interference in the memory system: application-aware memory channel partitioning (MCP), which maps the data of applications that are likely to severely interfere with each other to different memory channels.
Abstract: Main memory is a major shared resource among cores in a multicore system. If the interference between different applications' memory requests is not controlled effectively, system performance can degrade significantly. Previous work aimed to mitigate the problem of interference between applications by changing the scheduling policy in the memory controller, i.e., by prioritizing memory requests from applications in a way that benefits system performance.In this paper, we first present an alternative approach to reducing inter-application interference in the memory system: application-aware memory channel partitioning (MCP). The idea is to map the data of applications that are likely to severely interfere with each other to different memory channels. The key principles are to partition onto separate channels 1) the data of light (memory non-intensive) and heavy (memory-intensive) applications, 2) the data of applications with low and high row-buffer locality.Second, we observe that interference can be further reduced with a combination of memory channel partitioning and scheduling, which we call integrated memory partitioning and scheduling (IMPS). The key idea is to 1) always prioritize very light applications in the memory scheduler since such applications cause negligible interference to others, 2) use MCP to reduce interference among the remaining applications.We evaluate MCP and IMPS on a variety of multi-programmed workloads and system configurations and compare them to four previously proposed state-of-the-art memory scheduling policies. Averaged over 240 workloads on a 24-core system with 4 memory channels, MCP improves system throughput by 7.1% over an application-unaware memory scheduler and 1% over the previous best scheduler, while avoiding modifications to existing memory schedulers. IMPS improves system throughput by 11.1% over an application-unaware scheduler and 5% over the previous best scheduler, while incurring much lower hardware complexity than the latter.

281 citations