Gate recess structure engineering using silicon-nitride-assisted process for increased breakdown voltage in pseudomorphic HEMTs
TL;DR: In this paper, the authors reported the fabrication of pseudomorphic high electron mobility transistors (pHEMTs) with engineered recess structure of any width of choice, by a single lithography and etching step with the help of silicon-nitride-assisted process.
Abstract: We report the fabrication of pseudomorphic high electron mobility transistors (pHEMTs) with engineered recess structure of any width of choice, by a single lithography and etching step with the help of silicon-nitride-assisted process. In this process, a silicon nitride layer is deposited prior to gate lithography. First, the silicon nitride is etched by buffered hydrofluoric acid (BHF) in the gate opening and then selective recessing is performed. The recess base width can be engineered by varying etch time of silicon nitride in BHF. The base width increases linearly with etch time as shown by SEM. We demonstrate that the top photoresist gate opening that decides the gate length is unaffected by any duration of silicon nitride etch time. Thereby, we have engineered the distance from gate edge to n+-GaAs (Lgn+) which decides the gate-to-drain breakdown voltage (BVgd). With this method, BVgd?increased from 12 to 20?V as a function of Lgn+. The electric field distribution across the recess structure has been simulated to interpret this result. Since the high BVgd?of pHEMT is essential for power applications as well as switch applications, this method can be easily adopted even though the corresponding reduction in transconductance and unit current gain cut-off frequency (ft) is only marginal from 375 to 350 mS mm?1?and from 39 to 31?GHz, respectively.
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TL;DR: In this paper, electron microscopy techniques employing nanometer and sub-nanometer scale imaging capability of structure and chemistry have been widely used to characterise various aspects of electronic and optoelectronic device structures such as InAs and GaN nanowires.
Abstract: Microstructural and compositional characterisation of electronic materials in support of the development of GaAs, GaN and GaSb based multilayer device structures is described. Electron microscopy techniques employing nanometer and sub-nanometer scale imaging capability of structure and chemistry have been widely used to characterise various aspects of electronic and optoelectronic device structures such as InGaAs quantum dots, InGaAs pseudomorphic (pHEMT) and metamorphic (mHEMT) layers and the ohmic metallisation of GaAs and GaN high electron mobility transistors, nichrome thin film resistors, GaN heteroepitaxy on sapphire and silicon substrates, as well as InAs and GaN nanowires. They also established convergent beam electron diffraction techniques for determination of lattice distortions in III-V compound semiconductors, EBSD for crystalline misorientation studies of GaN epilayers and high-angle annular dark field techniques coupled with digital image analysis for the mapping of composition and strain in the nanometric layered structures. Also, in-situ SEM experiments were performed on ohmic metallisation of pHEMT device structures. The established electron microscopy expertise for electronic materials with demonstrated examples is presented.
2 citations
TL;DR: In this paper, a single mask processing technique for realizing double recess structure with the help of silicon nitride layer was presented, where two etching steps of silicon oxide and GaAs followed one after the other, generated the double recess structures, wherein the various etch times decide the width and shape of double recess.
Abstract: Monolithic microwave integrated circuits (MMICs) play an important part in today’s wireless communication electronics. GaAs-based pseudomorphic High Electron Mobility Transistor (pHEMT) is used in MMIC-based low noise amplifier (LNA) and power amplifier (PA) stages. The latter requires high device current ( I ds ) and high reverse breakdown voltage (BV gd ). In addition, the ON-state breakdown voltage should be high enough to operate the device at higher source–drain voltage ( V ds ). Double gate recessing is a well-established technique used to increase the ON and OFF-state breakdown voltages of a pHEMT device for power applications, which requires two levels of masking and recessing. In this paper, we present a single mask processing technique for realizing double recess structure with the help of silicon nitride layer. The new process involves deposition of silicon nitride after mesa isolation step of device fabrication. After gate lithography, two etching steps of silicon nitride and GaAs, followed one after the other, generates the double recess structure, wherein the various etch times decide the width and shape of double recess structure. The electric field distribution at the Schottky interface as well as along the channel has been simulated using ATLAS for the double recess structure used in this work. The fabricated recess structure showed improvement in breakdown voltage of the device which has been correlated to the effective redistribution of electric field in the device, as shown by simulation.
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TL;DR: The goal is to combine kinetic and kinematic data to examine translational motions during microgravity adaptations to encourage fine-control motions as these reduce the risk of injury and increase controllability.
Abstract: Introduction: Astronauts soaring through space modules with the grace of birds seems counterintuitive. How do they adapt to the weightless environment? Previous spaceflights have shown that astronauts in orbit adapt their motor strategies to each change in their gravitational environment. During adaptation, performance is degraded and can lead to mission-threatening injuries. If adaptation can occur before a mission, productivity during the mission might improve, minimizing risk. The goal is to combine kinetic and kinematic data to examine translational motions during microgravity adaptations. Methods: Experiments were performed during parabolic flights aboard NASA's C-9. Five subjects used their legs to push off from a sensor, landing on a target 3.96 m (13 ft) away. The sensor quantified the kinetics during contact, while four cameras recorded kinematics during push-off. Joint torques were calculated for a subset of traverses (N = 50) using the forces, moments, and joint angles. Results: During the 149 traverses, the average peak force exerted onto the sensor was 224.6 ± 74.6 N, with peak values ranging between 65.8―461.9 N. Two types of force profiles were observed, some having single, strong peaks (N = 64) and others having multiple, weaker peaks (N = 86). Conclusions: The force data were consistent with values recorded previously in sustained microgravity aboard Mir and the Space Shuttle. A training program for astronauts might be designed to encourage fine-control motions (i.e., multiple, weaker peaks) as these reduce the risk of injury and increase controllability. Additionally, a kinematic and kinetic sensor suite was successfully demonstrated in the weightless environment onboard the C-9 aircraft.
5,638 citations
TL;DR: In this paper, field effect transistors for logic applications, based on two representative two-dimensional (2D) materials, graphene and MoS2, are discussed, and the future developments in 2D material transistors are discussed.
Abstract: Field-effect transistors (FETs) for logic applications, based on two representative two-dimensional (2D) materials, graphene and MoS2, are discussed. These materials have drastically different properties and require different considerations. The unique band structure of graphene necessitates engineering of the Dirac point, including the opening of the bandgap, the doping and the interface, before the graphene can be used in logic applications. On the other hand, MoS2 is a semiconductor, and its electron transport depends heavily on the surface properties, the number of layers, and the carrier density. Finally, we discuss the prospects for the future developments in 2D material transistors.
314 citations
TL;DR: These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs, especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics.
Abstract: Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).
138 citations
TL;DR: In this article, a set of W-band power amplifier (PA) modules using monolithic microwave integrated circuits (MMICs) have been developed for the local oscillators of the far-infrared and sub-millimeter telescope (FIRST).
Abstract: A set of W-band power amplifier (PA) modules using monolithic microwave integrated circuits (MMICs) have been developed for the local oscillators of the far-infrared and sub-millimeter telescope (FIRST). The MMIC PA chips include three driver and three PAs, designed using microstrip lines, and another two smaller driver amplifiers using coplanar waveguides, covering the entire W-band. The highest frequency PA, which covers 100-113 GHz, has a peak power of greater than 250 mW (25 dBm) at 105 GHz, which is the best output power performance for a monolithic amplifier above 100 GHz to date. These monolithic PA chips are fabricated using 0.1-/spl mu/m AlGaAs/InGaAs/GaAs pseudomorphic T-gate power high electron-mobility transistors on a 2-mil GaAs substrate. The module assembly and testing, together with the system applications, is also addressed in this paper.
104 citations
Abstract: A new model for gate breakdown in MESFETs and HEMTs is presented. The model is based upon a combination of thermally assisted tunneling and avalanche breakdown. When thermal effects are considered it is demonstrated that the model predicts increasing drain-source breakdown as the gate electrode is biased towards pinch-off, in agreement with experimental data. The model also predicts the gate current versus bias behavior observed in experimental data. The model is consistent with various reports of breakdown and light emission phenomena reported in the literature. >
83 citations
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