Gate recess structure engineering using silicon-nitride-assisted process for increased breakdown voltage in pseudomorphic HEMTs
TL;DR: In this paper, the authors reported the fabrication of pseudomorphic high electron mobility transistors (pHEMTs) with engineered recess structure of any width of choice, by a single lithography and etching step with the help of silicon-nitride-assisted process.
Abstract: We report the fabrication of pseudomorphic high electron mobility transistors (pHEMTs) with engineered recess structure of any width of choice, by a single lithography and etching step with the help of silicon-nitride-assisted process. In this process, a silicon nitride layer is deposited prior to gate lithography. First, the silicon nitride is etched by buffered hydrofluoric acid (BHF) in the gate opening and then selective recessing is performed. The recess base width can be engineered by varying etch time of silicon nitride in BHF. The base width increases linearly with etch time as shown by SEM. We demonstrate that the top photoresist gate opening that decides the gate length is unaffected by any duration of silicon nitride etch time. Thereby, we have engineered the distance from gate edge to n+-GaAs (Lgn+) which decides the gate-to-drain breakdown voltage (BVgd). With this method, BVgd?increased from 12 to 20?V as a function of Lgn+. The electric field distribution across the recess structure has been simulated to interpret this result. Since the high BVgd?of pHEMT is essential for power applications as well as switch applications, this method can be easily adopted even though the corresponding reduction in transconductance and unit current gain cut-off frequency (ft) is only marginal from 375 to 350 mS mm?1?and from 39 to 31?GHz, respectively.
Citations
More filters
TL;DR: In this paper, electron microscopy techniques employing nanometer and sub-nanometer scale imaging capability of structure and chemistry have been widely used to characterise various aspects of electronic and optoelectronic device structures such as InAs and GaN nanowires.
Abstract: Microstructural and compositional characterisation of electronic materials in support of the development of GaAs, GaN and GaSb based multilayer device structures is described. Electron microscopy techniques employing nanometer and sub-nanometer scale imaging capability of structure and chemistry have been widely used to characterise various aspects of electronic and optoelectronic device structures such as InGaAs quantum dots, InGaAs pseudomorphic (pHEMT) and metamorphic (mHEMT) layers and the ohmic metallisation of GaAs and GaN high electron mobility transistors, nichrome thin film resistors, GaN heteroepitaxy on sapphire and silicon substrates, as well as InAs and GaN nanowires. They also established convergent beam electron diffraction techniques for determination of lattice distortions in III-V compound semiconductors, EBSD for crystalline misorientation studies of GaN epilayers and high-angle annular dark field techniques coupled with digital image analysis for the mapping of composition and strain in the nanometric layered structures. Also, in-situ SEM experiments were performed on ohmic metallisation of pHEMT device structures. The established electron microscopy expertise for electronic materials with demonstrated examples is presented.
2 citations
TL;DR: In this paper, a single mask processing technique for realizing double recess structure with the help of silicon nitride layer was presented, where two etching steps of silicon oxide and GaAs followed one after the other, generated the double recess structures, wherein the various etch times decide the width and shape of double recess.
References
More filters
TL;DR: In this article, the impact ionization and light emission in pseudomorphic AlGaAs/InGaAs HEMTs characterized by delta doping in the undoped AlGAAs layer and by additional planar doping within the InGaAs channel were studied.
Abstract: Impact ionization and light emission have been studied in pseudomorphic AlGaAs/InGaAs HEMTs characterized by delta doping in the undoped AlGaAs layer and by additional planar doping within the InGaAs channel, and suitable for high-power applications. Impact ionization has been demonstrated to the limiting effect for high V/sub ds/ applications. Emission spectra in the 1.1-2.6 eV range have been analyzed. They show peaks at low energy due to recombination mechanisms and a long tail due to hot electrons. >
70 citations
NEC1
TL;DR: In this paper, a simple recess structure without surface n+contact layer was investigated and it was found that the drain breakdown voltage was improved by increasing the thickness of the active epitaxial layer, due to relaxation of the field at the drain region.
Abstract: Dependence of the drain-to-source breakdown voltage on the drain structure of GaAs power FET's was investigated. It was found that the drain breakdown voltage is improved by a simple recess structure without surface n+contact layer. This is due to relaxation of the field at the drain region by increase of the thickness of the active epitaxial layer. The GaAs MESFET with this simple recess structure could be operated up to 24 V. There was no explicit difference in the microwave properties of both recess structure devices with and without the n+contact layer. As a practical device, an output power of more than 3 W with 4-dB gain is obtained at 6.5 GHz from this simple recess and cross-over structure GaAs FET.
66 citations
TL;DR: In this paper, the surface potential effect on gate-drain avalanche breakdown in GaAs MESFETs was investigated with a two-dimensional device simulator and two device structures producing high breakdown voltages, an offset gate structure and a recessed gate structure, were analyzed.
Abstract: The surface potential effect on gate-drain avalanche breakdown in GaAs MESFET's is investigated with a two-dimensional device simulator. It is shown that the surface potential effect changes the potential distribution in GaAs MESFET's drastically and therefore plays an important role in determining drain breakdown voltage. In addition, two device structures producing high breakdown voltages, an offset gate structure and a recessed gate structure, are analyzed.
65 citations
TL;DR: In this paper, the surface potential effect in GaAs MESFETs caused a depleted zone to form not only between the source and gate, but also between the gate and drain.
Abstract: The surface potential effect in GaAs MESFETs causes a depleted zone to form not only between the source and gate, but also between the gate and drain. The consequences of this phenomenon on the device behavior, the DC and AC characteristics, and the expected performance are studied. For this purpose, a two-dimensional resolution of the basic semiconductor equations is used. This model takes into account relaxation effects by including an energy relaxation equation. The dependence of MESFET characteristics such as transconductance, output conductance, and capacitance on the dimensions of the zone where surface potential effects occur is given. Some interesting conclusions concerning the optimization of recessed-gate structures are drawn. >
50 citations
TL;DR: In this article, the authors reviewed the literature dealing with off-state gate-drain breakdown in MESFET and HEMT structures, with particular emphasis on GaAs PHEMTs, in terms of the physics of the breakdown phenomenon; the breakdown walkout effect; the impact of design and process choices on the breakdown behavior; and the experimental techniques used for breakdown characterization.
Abstract: This paper reviews the literature dealing with off-state gate-drain breakdown in MESFET and HEMT structures, with particular emphasis on GaAs PHEMTs, in terms of: 1) the physics of the breakdown phenomenon; 2) the breakdown walkout effect; 3) the impact of design and process choices on the breakdown behavior; and 4) the experimental techniques used for breakdown characterization. A thorough temperature-dependent breakdown characterization of commercial PHEMTs is also shown and discussed. It is found that different physical mechanisms may dominate the gate-drain leakage depending on the reverse bias and temperature range considered, and the particular PHEMT technology. The main results shown here tell us the following. 1) The breakdown voltages are decreasing functions of temperature between room temperature and 160/spl deg/C. 2) Between room temperature and 90-100/spl deg/C, thermionic-field emission seems be dominant, with low activation energies below 0.15 eV; as a consequence, the temperature dependence of the breakdown voltage is weak. 3) Between 110/spl deg/C and 160/spl deg/C, higher activation energy mechanisms (possibly trap-assisted tunneling and thermionic emission over a field-dependent barrier) tend to dominate, and the temperature dependence of the breakdown voltages is stronger.
48 citations