Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric
TL;DR: In this article, a study on Ge diffusion and its impact on the electrical properties of TaN∕HfO2∕Ge metal-oxide-semiconductor (MOS) device is presented.
Abstract: We report a study on Ge diffusion and its impact on the electrical properties of TaN∕HfO2∕Ge metal-oxide-semiconductor (MOS) device. It is found that Ge diffusion depends on the amount of GeO2 formed at the HfO2∕Ge interface and can be retarded by surface nitridation. It is speculated that Ge diffusion is in the form of GeO or Ge-riched HfGeO. Effective suppression of Ge diffusion by NH3 nitridation has resulted in improved electrical properties of TaN∕HfO2∕Ge MOS device, including equivalent oxide thickness (EOT), leakage current, hysteresis, and interface state density. The degradation of leakage current after high temperature post metallization anneal (PMA) is found to be due to Ge diffusion.
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TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations
TL;DR: In this article, a review of the most commonly used germanium surface passivation methods (e.g., epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics is presented.
Abstract: Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately??2 for electrons and??4 for holes when compared to conventional Si channels) However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments It is observed that each process step can significantly affect the overall metal?oxide?semiconductor (MOS)-FET device performance In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (eg epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures To further improve properties, the gate stack can be annealed after deposition The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed
132 citations
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
128 citations
Cites background from "Ge diffusion in Ge metal oxide semi..."
...The most common are chemical vapor deposition (CVD) [77,78], physical vapor deposition (PVD) [79], molecular beam...
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...The most common are chemical vapor deposition (CVD) [77,78], physical vapor deposition (PVD) [79], molecular beam deposition (MDB) [80,81], and atomic layer deposition (ALD) (two variations: thermal [82], and plasma [83])....
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...Other approaches exist, such as surface nitridation [77], and sulfur passivation [109], however these approaches are not reviewed in this paper....
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TL;DR: A review of the current status for atomic layer deposited high-κ dielectrics on Ge and III-V channel materials is presented in this paper, with a focus on the use of deposited gate dielectric in large-scale production for Si-based integrated circuits.
Abstract: The prospect of utilizing alternative transistor channel materials for ultrahigh performance transistors will require suitable gate dielectrics for surface-channel field-effect devices. With the utilization of deposited gate dielectrics in large-scale production for Si-based integrated circuits by atomic layer deposition, extending this technology to channel materials that exhibit high bulk mobility behavior is of interest. A review of the current status for atomic layer deposited high-κ dielectrics on Ge and III–V channel materials is presented.
105 citations
TL;DR: In this article, the physical and electrical properties of Ge MIS interfaces fabricated by direct oxidation and nitridation of Ge surfaces are reviewed and compared on gate stacks composing of HfO"2 and the nitrided Ge surfaces.
99 citations
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TL;DR: In this article, the M-O-S diode was introduced, and a theory for its operation in the absence of surface states was obtained, and it was shown that surface states with non-zero relaxation times may increase the capacitance of the device, as well as affect the proportion of applied voltage which appears across the silicon.
Abstract: A new solid-state device, the M-O-S diode, of which an oxidized silicon surface is an integral part, is introduced, and a theory for its operation in the absence of surface states is obtained. The capacitance of this device may be considerably more voltage sensitive than that of a p-n junction. The existence of surface states with non-zero relaxation times is introduced into the theoretical model. It is shown that the states may increase the capacitance of the device, as well as affect the proportion of applied voltage which appears across the silicon. A small-signal equivalent circuit is derived which includes the effect of the surface states. It is also shown that a comparison of the theoretical capacitance vs. voltage curve without states and a measured high-frequency capacitance vs. voltage curve may be used to obtain the distribution of all states, regardless of their time constants. Results are given of measurements and calculations on two M-O-S diodes having different surface treatments before oxidation. Both surfaces have a total density of about 3 × 10 12 states/cm 2 . In both cases, the distribution of states is continuous and has its highest peak about 100 mV above E F (0), the position of the Fermi level at the silicon surface if there is no voltage drop across the silicon The time constants of the states extend from 10 −8 sec to longer than 10 −2 sec. There is a tendency for states located at deeper energy levels to have longer time constants, but some of the states in the high density of states above E F (0) have long time constants. The distribution of time constants with energy level is somewhat different for the two surfaces. A comparison is made between the distribution of states obtained here with the distribution reported by others working in the field. The results are similar in density and location of the peaks of the distribution reported here, but differ in that some other sources report a discrete distribution.
1,331 citations
TL;DR: In this paper, the thermal decomposition pathway of an ultrathin oxide layer on Ge(100) and Si (100) surfaces is examined by synchrotron radiation photoelectron spectroscopy and ultraviolet photo-electron Spectroscopy with helium I radiation.
Abstract: The thermal decomposition pathway of an ultrathin oxide layer on Ge(100) and Si(100) surfaces is examined by synchrotron radiation photoelectron spectroscopy and ultraviolet photoelectron spectroscopy with helium I radiation. The as-prepared oxide layer consists of a mixture of oxides, namely, suboxides and dioxides, on both the surfaces. Upon annealing, the oxide layers decompose and desorb as monoxides. However, we find that the decomposition pathways are different from each other. On annealing Ge oxides, GeO2 species transform to GeO and remain on the surface and desorb at >420 °C. In contrast, annealing of Si oxides results in the transformation of SiO to SiO2 up to temperatures (∼780 °C) close to the desorption. At higher temperatures, SiO2 decomposes and desorbs, implying a reverse transformation to volatile SiO species.
251 citations
08 Dec 2002
TL;DR: In this article, a low thermal budget germanium MOS process with high/spl kappa/ gate dielectric and metal gate electrode has been demonstrated, and self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate have been demonstrated with equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode.
Abstract: A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.
128 citations
TL;DR: In this article, a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectrics-Ge capacitors was carried out.
Abstract: We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.
120 citations
TL;DR: An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied in this paper, where surface SiH4 annealing was implemented prior to HfO2 deposition.
Abstract: An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied The surface SiH4 annealing was implemented prior to HfO2 deposition X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition The electrical measurement shows that an equivalent oxide thickness of 135A and a leakage current of 116×10−5A∕cm2 at 1V gate bias was achieved for TaN∕HfO2∕Ge MOS capacitors with the SiH4 surface treatment
118 citations