Genetic Algorithm PDN Optimization based on Minimum Number of Decoupling Capacitors Applied to Arbitrary Target Impedance
01 Jul 2020-
TL;DR: An optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution is proposed, leading to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location.
Abstract: The current demand in Power Distribution Network (PDN) design is characterized by the accurate placement of decoupling capacitors and the minimization of their number aimed at cost saving. The paper proposes an optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution. This allows the designer to identify the minimum number of decaps whenever the input impedance satisfies the target impedance requirements. The algorithm is based on the Genetic Algorithm accordingly adapted for the specific application of PDN design. It may involve the evaluation of the input impedance at multiple locations, representing either multiple ICs, as well as multiple power input areas/pins of the same IC. The validation of the developed optimization algorithm is carried out by applying it to a manufactured PCB and by employing typical (low inductance) decaps for PDN design. The optimization process led to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location. An accurate experimental test further validates the optimized PDN.
Citations
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TL;DR: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm and Artificial Neural Network to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators.
Abstract: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm (GA) and Artificial Neural Network (ANN). The ANN is first trained by an appropriate set of results obtained by a commercial simulator. Once the ANN is ready, it is used within an iterative GA process to place a minimum number of decoupling capacitors for minimizing the differences between the input impedance at one or more location, and the required target impedance. The combined GA–ANN process is shown to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators. With the new approach the accuracy of the results remains at the same level, but the computational time is reduced by at least 30 times. Two test cases have been considered for validating the proposed approach, with the second one also being compared by experimental measurements.
12 citations
TL;DR: In this article, the authors proposed a jitter-aware decoupling capacitors placement optimization method that uses the genetic algorithm (GA) for power source-induced jitter (PSIJ) optimization based on the GA-based tool.
Abstract: This article proposes a jitter-aware decoupling capacitors placement optimization method that uses the genetic algorithm (GA). A novel method for defining the optimization target function in regard to power delivery network (PDN) and power source-induced jitter (PSIJ) optimization based on the GA-based tool is proposed. The proposed method can provide an optimum and economic solution for the number of decoupling capacitors to use in a PDN to reach the target impedance. Then, by modifying the optimization target function with our proposed method, an optimum solution of the number of decoupling capacitors regarding the PSIJ can be obtained. The PSIJ analytical expressions are derived in conjunction with a resonant cavity model that includes the coordinates of the decoupling capacitors and the PSIJ transfer function. The GA-based optimization algorithm with the proposed target function is first applied to optimize the number of decoupling capacitors regarding the PSIJ. Finally, the measured jitters from HSPICE simulation results are used to verify our optimization method such that both the simulated results and analytically calculated results support the efficiency of our proposed optimization method.
9 citations
TL;DR: In this article , a multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs).
Abstract: A multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs). The proposed method is based on barrier methods and can simultaneously handle multiple ball grid array (BGA) devices and capacitor ports on practical power/ground plane pairs of polygonal shapes without restriction in the problem geometry. Semi-analytical expressions are developed for the magnitude of device port impedance that is set as the objective function. The placement optimization problem including constraints of planar boundaries and impedance specifications is cast into a matrix expression that meets Karush–Kuhn Tucker (KKT) conditions and solved through Newton–Raphson (N–R) iterations. The convergence of iterations is ensured by guaranteeing the positive definiteness of the system matrix through the Levenberg–Marquardt algorithm. Mutual coupling among multiple ports and discrete components of the problem domain is accounted for via matrix calculus techniques applied to the partial derivatives of optimization variables. The derivatives are evaluated accurately exploiting the semi-analytical relations developed for the distributed planar impedance. The proposed method is tested with several examples, and the results are observed to be in good agreement with those obtained from a numerical electromagnetic (EM) simulator while yielding significant speed-up.
2 citations
TL;DR: In this paper , a power delivery network (PDN) noise absorber is applied to the power system and verified based on a power trace system, and the power integrity performance of this prototype was compared with two other cases, power trace only and power trace with a de-cap.
Abstract: In this article, for the first time, a power delivery network (PDN) noise absorber is applied to the power system and verified based on a power trace system. Among all the existing absorptive circuits, a low-pass reflectionless circuit is chosen as our PDN noise absorber due to its broadband characteristic. Since the speed of the signal becomes higher and higher nowadays, a millimeter distance of a power trace with the traditional reflective PDN noise suppression devices, such as decoupling capacitors (de-caps), may provide serious standing wave on it and seriously affect the system. The proposed PDN noise absorber, on the other hand, can absorb the PDN noises so that the standing wave on the power trace can be prevented. This makes power trace systems more stable and avoids significant power noises at some locations. A prototype using a PDN noise absorber was fabricated. The power integrity performance of this prototype was compared with two other cases, power trace only and power trace with a de-cap. Compared with the de-cap case at the designed frequency 750 MHz, a PDN noise absorber can reduce 40% maximum voltage ripple. On the other hand, noise coupling between the digital and radio frequency circuits has also been demonstrated and compared for those three different PDNs. It shows a 3.7-dB decrease in gain fluctuation for the PDN with power noise absorber compared with the de-cap case. According to these results, no matter from power integrity or noise coupling suppression viewpoint, PDN noise absorber can be a good candidate to make the power system more stable.
1 citations
TL;DR: Extensive experiments verified that CSE with zero-shot inference outperforms the neural baselines and iterative conventional design methods on the DPP benchmark, and CSE greatly outperformed the expert method used to generate the offline data for training.
Abstract: This paper proposes collaborative symmetricity exploitation (CSE) framework to train a solver for the decoupling capacitor placement problem (DPP), one of the significant hardware design problems. Due to the sequentially coupled multi-level property of the hardware design process, the design condition of DPP changes depending on the design of higher-level problems. Also, the online evaluation of real-world electrical performance through simulation is extremely costly. Thus, we propose the CSE framework that allows data-efficient offline learning of a DPP solver (i.e., contextualized policy) with high generalization capability over changing task conditions. Leveraging the symmetricity for offline learning of hardware design solver increases data-efficiency by reducing the solution space and improves generalization capability by capturing the invariant nature present regardless of changing conditions. Extensive experiments verified that CSE with zero-shot inference outperforms the neural baselines and iterative conventional design methods on the DPP benchmark. Furthermore, CSE greatly outperformed the expert method used to generate the offline data for training.
References
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TL;DR: In this article, a methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented.
Abstract: A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.
31 citations
27 May 2014
TL;DR: This paper proposes a modified target impedance method that significantly reduces the pessimism built into the originaltarget impedance method and a real FPGA decoupling case is used to demonstrate the effectiveness of this proposal.
Abstract: Decoupling core power for modern processors or SOCs is a challenging task due to large power consumption. The decoupling network designed by a commonly used target impedance approach is known to be very pessimistic and very difficult to implement. In this paper, a step surge current is identified as a major source of core power noise. By considering the ramp time of the surge current, we propose a modified target impedance method that significantly reduces the pessimism built into the original target impedance method. As an example, a real FPGA decoupling case is used to demonstrate the effectiveness of the new proposal.
21 citations
TL;DR: The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk.
Abstract: A multiobjective evolutionary method is proposed for the optimization of surface mount device (SMD) multilayer ceramic chip (MLCC) capacitors used for decoupling on printed circuit boards (PCBs) with resonant power–ground plane pairs. The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk. It is also shown that uniform MLCC capacitors with variable distance from power pins can have a similar decoupling effect to an assortment of capacitors. By simultaneously optimizing the pin-capacitor distance and value, the proposed method is shown to allow for the allocation of fewer decoupling capacitors under the ball-grid-array (BGA) pin field of an integrated circuit (IC) device.
20 citations
TL;DR: In this article, fast capacitor assignment algorithms capable of finding a decoupling solution scheme with a minimum number of components that meets a predefined target impedance with a semi-arbitrary shape within a few seconds to an hour for a given power distribution network (PDN) are proposed.
Abstract: In this paper, fast capacitor assignment algorithms capable of finding a decoupling solution scheme with a minimum number of components that meets a predefined target impedance with a semi-arbitrary shape within a few seconds to an hour for a given power distribution network (PDN) are proposed. The proposed algorithms also provide identification of shadowed decap ports in a PDN based on an inductance matrix extraction from the given PDN model. Elimination of those shadowed decap ports with the proposed algorithms enables more effective layouts and cost savings on PCB designs.
20 citations
01 Oct 2007
TL;DR: Removal of members of population having certain percentage of similarity would keep GA perform better, balancing and maintaining convergence property intact as well as avoids stalling.
Abstract: The schemata theorem, on which the working of Genetic Algorithm (GA) is based in its current form, has a fallacious selection procedure and incomplete crossover operation. In this paper, generalization of the schemata theorem has been provided by correcting and removing these limitations. The analysis shows that similarity growth within GA population is inherent due to its stochastic nature. While the stochastic property helps in GA's convergence. The similarity growth is responsible for stalling and becomes more prevalent for hard optimization problem like protein structure prediction (PSP). While it is very essential that GA should explore the vast and complicated search landscape, in reality, it is often stuck in local minima. This paper shows that, removal of members of population having certain percentage of similarity would keep GA perform better, balancing and maintaining convergence property intact as well as avoids stalling.
18 citations