Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, the impact of constant voltage stress (CVS) on trapped charges results in variation of threshold voltage (Vth) and hysteresis window (W) were studied.
Abstract: The quest for the high speed, low power digital logic circuits urge an imperative demand of compatible high-κ dielectric integration on novel Germanium (Ge) based channel material. Here, first ever a methodical nanoscopic and microscopic probes were attempted to Atomic Layer Deposited, Hafnium Dioxide (HfO2) dielectrics on Molecular Beam Epitaxy (MBE) of p-Ge-on-p-Si stack. Kelvin Probe Force Microscopy based contact potential difference (CPD) analysis reveals that the disintegration of trapped charges lasting for ∼18 hours. The impact of constant voltage stress (CVS) on trapped charges results in variation of threshold voltage (Vth) and hysteresis window (W) were studied. The cyclic Capacitance-Voltage (C-V) characteristics at 0.5 MHz exhibit the shift in the flat band (ΔVfb), ΔVth, and ΔW at 10V stress were ∼0.84V, ∼0.62V, and ∼0.47V, respectively. While the computed interface trap density (Dit) and total effective charge density (Qeff) were ∼8.49 × 1012 eV−1cm−2 and ∼1.81 × 1012 cm−2, respectively. The gate leakage current density, (J) at 5V is 26.53 × 10−6 A/cm2 and reduced by a factor of ∼6.8 after 10V, CVS. Whereas the current density (J) increases from ∼26.53 × 10−6 A/cm2 at 25 °C by a factor of ∼2 at 125 °C. To study the retention and effect of charge trapping, the stress-time analysis was performed for 8000s at 3V (CVS). The r.m.s. surface roughness of HfO2 thin films was found to be ∼0.23 nm. X-ray photoelectron spectroscopy (XPS) depth profiling categorized the elemental composition of thin films. These investigations would help to HfO2/p-Ge-on-p-Si system interfacial engineering well before the Ge based nano device realization.
11 citations
TL;DR: In this article, the influence of the recrystallization mechanism and co-doping of Sn on the carrier distribution and carrier mobility both in n-type and p-type GeOI wafers is discussed in detail.
Abstract: We present the development, optimization and fabrication of high carrier mobility materials based on GeOI wafers co-doped with Sn and P. The Ge thin films were fabricated using plasma-enhanced chemical vapour deposition followed by ion implantation and explosive solid phase epitaxy, which is induced by millisecond flash lamp annealing. The influence of the recrystallization mechanism and co-doping of Sn on the carrier distribution and carrier mobility both in n-type and p-type GeOI wafers is discussed in detail. This finding significantly contributes to the state-of-the-art of high carrier mobility-GeOI wafers since the results are comparable with GeOI commercial wafers fabricated by epitaxial layer transfer or SmartCut technology.
10 citations
TL;DR: In this paper, the formation of low resistivity ohmic contacts in highly n-type doped Ge via non-equilibrium thermal processing consisting of millisecond-range flash lamp annealing is reported.
Abstract: Highly scaled nanoelectronics requires effective channel doping above 5 × 1019 cm−3 together with ohmic contacts with extremely low specific contact resistivity. Nowadays, Ge becomes very attractive for modern optoelectronics due to the high carrier mobility and the quasi-direct bandgap, but n-type Ge doped above 5 × 1019 cm−3 is metastable and thus difficult to be achieved. In this letter, we report on the formation of low-resistivity ohmic contacts in highly n-type doped Ge via non-equilibrium thermal processing consisting of millisecond-range flash lamp annealing. This is a single-step process that allows for the formation of a 90 nm thick NiGe layer with a very sharp interface between NiGe and Ge. The measured carrier concentration in Ge is above 9 × 1019 cm−3 with a specific contact resistivity of 1.2 × 10−6 Ω cm2. Simultaneously, both the diffusion and the electrical deactivation of P are fully suppressed.
10 citations
TL;DR: Detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge by atomic layer deposition shows extremely low gate leakage, small and scalable EOT, and good and reducible D(it).
Abstract: Germanium (Ge)-based metal–oxide–semiconductor field-effect transistors are a promising candidate for high performance, low power electronics at the 7 nm technology node and beyond. However, the availability of high quality gate oxide/Ge interfaces that provide low leakage current density and equivalent oxide thickness (EOT), robust scalability, and acceptable interface state density (Dit) has emerged as one of the most challenging hurdles in the development of such devices. Here we demonstrate and present detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge (001) by atomic layer deposition. Metal–oxide–Ge capacitor structures show extremely low gate leakage, small and scalable EOT, and good and reducible Dit. Detailed growth strategies and postgrowth annealing schemes are demonstrated to reduce Dit. The physical mechanisms behind these phenomena are studied and suggest approaches for further reduction of Dit.
9 citations
TL;DR: In this paper, a Map of Interfacial Periodicity (MIMO) is used to visualize and classify the periodicity at hetero-phase boundaries, which is a necessary condition to achieve an optimized bonding arrangement across the interface.
9 citations
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04 Jul 1990
TL;DR: In this article, the authors present a characterization of the resistivity of a two-point-versus-four-point probe in terms of the number of contacts and the amount of contacts in the probe.
Abstract: Preface to Third Edition. 1 Resistivity. 1.1 Introduction. 1.2 Two-Point Versus Four-Point Probe. 1.3 Wafer Mapping. 1.4 Resistivity Profiling. 1.5 Contactless Methods. 1.6 Conductivity Type. 1.7 Strengths and Weaknesses. Appendix 1.1 Resistivity as a Function of Doping Density. Appendix 1.2 Intrinsic Carrier Density. References. Problems. Review Questions. 2 Carrier and Doping Density. 2.1 Introduction. 2.2 Capacitance-Voltage (C-V). 2.3 Current-Voltage (I-V). 2.4 Measurement Errors and Precautions. 2.5 Hall Effect. 2.6 Optical Techniques. 2.7 Secondary Ion Mass Spectrometry (SIMS). 2.8 Rutherford Backscattering (RBS). 2.9 Lateral Profiling. 2.10 Strengths and Weaknesses. Appendix 2.1 Parallel or Series Connection? Appendix 2.2 Circuit Conversion. References. Problems. Review Questions. 3 Contact Resistance and Schottky Barriers. 3.1 Introduction. 3.2 Metal-Semiconductor Contacts. 3.3 Contact Resistance. 3.4 Measurement Techniques. 3.5 Schottky Barrier Height. 3.6 Comparison of Methods. 3.7 Strengths and Weaknesses. Appendix 3.1 Effect of Parasitic Resistance. Appendix 3.2 Alloys for Contacts to Semiconductors. References. Problems. Review Questions. 4 Series Resistance, Channel Length and Width, and Threshold Voltage. 4.1 Introduction. 4.2 PN Junction Diodes. 4.3 Schottky Barrier Diodes. 4.4 Solar Cells. 4.5 Bipolar Junction Transistors. 4.6 MOSFETS. 4.7 MESFETS and MODFETS. 4.8 Threshold Voltage. 4.9 Pseudo MOSFET. 4.10 Strengths and Weaknesses. Appendix 4.1 Schottky Diode Current-Voltage Equation. References. Problems. Review Questions. 5 Defects. 5.1 Introduction. 5.2 Generation-Recombination Statistics. 5.3 Capacitance Measurements. 5.4 Current Measurements. 5.5 Charge Measurements. 5.6 Deep-Level Transient Spectroscopy (DLTS). 5.7 Thermally Stimulated Capacitance and Current. 5.8 Positron Annihilation Spectroscopy (PAS). 5.9 Strengths and Weaknesses. Appendix 5.1 Activation Energy and Capture Cross-Section. Appendix 5.2 Time Constant Extraction. Appendix 5.3 Si and GaAs Data. References. Problems. Review Questions. 6 Oxide and Interface Trapped Charges, Oxide Thickness. 6.1 Introduction. 6.2 Fixed, Oxide Trapped, and Mobile Oxide Charge. 6.3 Interface Trapped Charge. 6.4 Oxide Thickness. 6.5 Strengths and Weaknesses. Appendix 6.1 Capacitance Measurement Techniques. Appendix 6.2 Effect of Chuck Capacitance and Leakage Current. References. Problems. Review Questions. 7 Carrier Lifetimes. 7.1 Introduction. 7.2 Recombination Lifetime/Surface Recombination Velocity. 7.3 Generation Lifetime/Surface Generation Velocity. 7.4 Recombination Lifetime-Optical Measurements. 7.5 Recombination Lifetime-Electrical Measurements. 7.6 Generation Lifetime-Electrical Measurements. 7.7 Strengths and Weaknesses. Appendix 7.1 Optical Excitation. Appendix 7.2 Electrical Excitation. References. Problems. Review Questions. 8 Mobility. 8.1 Introduction. 8.2 Conductivity Mobility. 8.3 Hall Effect and Mobility. 8.4 Magnetoresistance Mobility. 8.5 Time-of-Flight Drift Mobility. 8.6 MOSFET Mobility. 8.7 Contactless Mobility. 8.8 Strengths and Weaknesses. Appendix 8.1 Semiconductor Bulk Mobilities. Appendix 8.2 Semiconductor Surface Mobilities. Appendix 8.3 Effect of Channel Frequency Response. Appendix 8.4 Effect of Interface Trapped Charge. References. Problems. Review Questions. 9 Charge-based and Probe Characterization. 9.1 Introduction. 9.2 Background. 9.3 Surface Charging. 9.4 The Kelvin Probe. 9.5 Applications. 9.6 Scanning Probe Microscopy (SPM). 9.7 Strengths and Weaknesses. References. Problems. Review Questions. 10 Optical Characterization. 10.1 Introduction. 10.2 Optical Microscopy. 10.3 Ellipsometry. 10.4 Transmission. 10.5 Reflection. 10.6 Light Scattering. 10.7 Modulation Spectroscopy. 10.8 Line Width. 10.9 Photoluminescence (PL). 10.10 Raman Spectroscopy. 10.11 Strengths and Weaknesses. Appendix 10.1 Transmission Equations. Appendix 10.2 Absorption Coefficients and Refractive Indices for Selected Semiconductors. References. Problems. Review Questions. 11 Chemical and Physical Characterization. 11.1 Introduction. 11.2 Electron Beam Techniques. 11.3 Ion Beam Techniques. 11.4 X-Ray and Gamma-Ray Techniques. 11.5 Strengths and Weaknesses. Appendix 11.1 Selected Features of Some Analytical Techniques. References. Problems. Review Questions. 12 Reliability and Failure Analysis. 12.1 Introduction. 12.2 Failure Times and Acceleration Factors. 12.3 Distribution Functions. 12.4 Reliability Concerns. 12.5 Failure Analysis Characterization Techniques. 12.6 Strengths and Weaknesses. Appendix 12.1 Gate Currents. References. Problems. Review Questions. Appendix 1 List of Symbols. Appendix 2 Abbreviations and Acronyms. Index.
6,573 citations
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...
5,711 citations
TL;DR: In this paper, the surface chemistry of the trimethylaluminum/water ALD process is reviewed, with an aim to combine the information obtained in different types of investigations, such as growth experiments on flat substrates and reaction chemistry investigation on high-surface-area materials.
Abstract: Atomic layer deposition(ALD), a chemical vapor deposition technique based on sequential self-terminating gas–solid reactions, has for about four decades been applied for manufacturing conformal inorganic material layers with thickness down to the nanometer range. Despite the numerous successful applications of material growth by ALD, many physicochemical processes that control ALD growth are not yet sufficiently understood. To increase understanding of ALD processes, overviews are needed not only of the existing ALD processes and their applications, but also of the knowledge of the surface chemistry of specific ALD processes. This work aims to start the overviews on specific ALD processes by reviewing the experimental information available on the surface chemistry of the trimethylaluminum/water process. This process is generally known as a rather ideal ALD process, and plenty of information is available on its surface chemistry. This in-depth summary of the surface chemistry of one representative ALD process aims also to provide a view on the current status of understanding the surface chemistry of ALD, in general. The review starts by describing the basic characteristics of ALD, discussing the history of ALD—including the question who made the first ALD experiments—and giving an overview of the two-reactant ALD processes investigated to date. Second, the basic concepts related to the surface chemistry of ALD are described from a generic viewpoint applicable to all ALD processes based on compound reactants. This description includes physicochemical requirements for self-terminating reactions,reaction kinetics, typical chemisorption mechanisms, factors causing saturation, reasons for growth of less than a monolayer per cycle, effect of the temperature and number of cycles on the growth per cycle (GPC), and the growth mode. A comparison is made of three models available for estimating the sterically allowed value of GPC in ALD. Third, the experimental information on the surface chemistry in the trimethylaluminum/water ALD process are reviewed using the concepts developed in the second part of this review. The results are reviewed critically, with an aim to combine the information obtained in different types of investigations, such as growth experiments on flat substrates and reaction chemistry investigation on high-surface-area materials. Although the surface chemistry of the trimethylaluminum/water ALD process is rather well understood, systematic investigations of the reaction kinetics and the growth mode on different substrates are still missing. The last part of the review is devoted to discussing issues which may hamper surface chemistry investigations of ALD, such as problematic historical assumptions, nonstandard terminology, and the effect of experimental conditions on the surface chemistry of ALD. I hope that this review can help the newcomer get acquainted with the exciting and challenging field of surface chemistry of ALD and can serve as a useful guide for the specialist towards the fifth decade of ALD research.
2,212 citations
TL;DR: In this paper, the Schottky barrier heights and band offsets for high dielectric constant oxides on Pt and Si were calculated and good agreement with experiment is found for barrier heights.
Abstract: Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.
1,947 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...Both the conduction and valence band offsets (CBO and VBO respectively) must be at least 1 eV in order to suppress Schottky emission of electrons or holes into the oxide bands (another source of leakage current) [96]....
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TL;DR: It is shown that the islands formed in Stranski-Krastanow (SK) growth of Ge on Si(100) are initially dislocation free, and the limiting critical thickness of coherent SK islands is shown to be higher than that for 2D growth.
Abstract: We show that the islands formed in Stranski-Krastanow (SK) growth of Ge on Si(100) are initially dislocation free. Island formation in true SK growth should be driven by strain relaxation in large, dislocated islands. Coherent SK growth is explained in terms of elastic deformation around the islands, which partially accommodates mismatch. The limiting critical thickness, ${\mathit{h}}_{\mathit{c}}$, of coherent SK islands is shown to be higher than that for 2D growth. We demonstrate growth of dislocation-free Ge islands on Si to a thickness of \ensuremath{\approxeq}500 \AA{}, 50\ifmmode\times\else\texttimes\fi{}higher than ${\mathit{h}}_{\mathit{c}}$ for 2D Ge/Si epitaxy.
1,751 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...This strain energy is primarily relieved by two mechanisms: (i) generation of lattice dislocations at the interface (misfit dislocations) and (ii) elastic deformation of both the substrate and the Ge islands which form on the surface during early stages of growth (following the Stranski-Krastanow growth mode) [32]....
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