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Journal ArticleDOI

Germanium Based Field-Effect Transistors: Challenges and Opportunities

19 Mar 2014-Materials (MDPI AG)-Vol. 7, Iss: 3, pp 2301-2339
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

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Citations
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Journal ArticleDOI
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

512 citations

Journal ArticleDOI
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

116 citations

Journal ArticleDOI
17 Jan 2017-ACS Nano
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...

73 citations

Journal ArticleDOI
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.

65 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

49 citations

References
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Journal ArticleDOI
TL;DR: In this paper, the physical and electrical properties of Ge/GeO 2 /high-κ gate stacks, where the GeO 2 interlayer is thermally grown in molecular oxygen, are investigated.
Abstract: The physical and electrical properties of Ge/GeO 2 /high-κ gate stacks, where the GeO 2 interlayer is thermally grown in molecular oxygen, are investigated. The high-K layer (ZrO 2 , HfO 2 , or Al 2 O 3 ) is deposited in situ on the GeO 2 interlayer by atomic layer deposition. Detailed analysis of the capacitance-voltage and conductance-frequency characteristics of these devices provides evidence for the efficient passivation of the Ge(100) surface by its thermal oxide layer. A larger flatband voltage hysteresis is observed in HfO 2 -based gate stacks, as compared to Al 2 O 3 gate stacks, which is possibly related to the more pronounced intermixing observed between the HfO 2 and GeO 2 .

117 citations

Journal ArticleDOI
TL;DR: In this article, low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti have been reported on epitaxial n+-Ge (2.5×1019 cm−3) layers.
Abstract: We report low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti. A 350°C post metallization anneal is used to create oxygen vacancies that dope ZnO heavily n-type (n+). Rectifying Ti/n-Ge contacts become Ohmic with 1000× higher reverse current density after insertion of n+-ZnO IL. Specific resistivity of ∼1.4×10−7 Ω cm2 is demonstrated on epitaxial n+-Ge (2.5×1019 cm−3) layers. Low resistance with ZnO IL can be attributed to (a) low barrier height from Fermi-level unpinning, (b) good conduction band alignment between ZnO and Ge, and (c) thin tunneling barrier due to the n+ doping.

117 citations


"Germanium Based Field-Effect Transi..." refers background in this paper

  • ...There are, however, significant additional engineering challenges to achieving this, such as overcoming Ge’s tendency for have a higher interface state density (Dit) near the conduction band edge [21,22] and developing low resistance ohmic contacts to n-type Ge [23,24]....

    [...]

  • ...Ge n-channel devices continue to lag behind, but are also making progress due to improved ohmic contacts [24,145]....

    [...]

  • ...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....

    [...]

Journal ArticleDOI
TL;DR: In this paper, the authors proposed to insert ultrathin dielectrics at the metal-semiconductor interface to reduce tunneling resistance from the large conduction band offset (CBO) between the insulator and Ge.
Abstract: Metal contacts to n-type Ge have poor performance due to the Fermi level pinning near the Ge valence band at metal/Ge interfaces. The electron barrier height can be reduced by inserting ultrathin dielectrics at the metal-semiconductor interface. However, this technique introduces tunneling resistance from the large conduction band offset (CBO) between the insulator and Ge. In this work, the CBO between TiO2 and Ge is estimated to range from −0.06 to −0.26 eV so tunneling resistance can be reduced. By inserting 7.1 nm TiO2 between Al and n-Ge, current densities increased by about 900× at 0.1 V and 1200× at −0.1 V compared to contacts without TiO2.

114 citations


"Germanium Based Field-Effect Transi..." refers background in this paper

  • ...Recently, Zhang et al. [13] demonstrated an EOT of 0.65 nm using a gate stack of TiO2/Al2O3/Ge....

    [...]

  • ...Crystallographic-orientation agnostic TiO2-based MIS contacts may be particularly useful in the next generation of Ge FinFETs, where different Ge orientations can be exploited to facilitate mobility enhancement for n- and p-channel devices [148]....

    [...]

  • ...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....

    [...]

  • ...For this work, a fair leakage current of about 1 × 10 −2 A/cm 2 at Vg = −1 V is reported for the combined TiO2/Al2O3/Ge stack....

    [...]

  • ...It has been recently reported that the lower CBOs obtained for the crystallographic oriented TiO2/Ge system, irrespective of the Ge crystallographic orientation, presents a potential for employing a TiO2 insulating layer for MIS contact applications....

    [...]

Journal ArticleDOI
TL;DR: In this article, a detailed analysis of the mechanisms by which dislocation elimination is achieved has been carried out and it has been shown that facets play a dominant role in determining the configurations of threading dislocations in the films.
Abstract: Recent research has demonstrated the effectiveness of the “aspect ratio trapping” technique for eliminating threading dislocations in Ge grown selectively in submicron trenches on Si substrates. In this letter, analysis of the mechanisms by which dislocation elimination is achieved has been carried out. Detailed transmission electron microscopy studies reveal that facets, when formed early in the growth process, play a dominant role in determining the configurations of threading dislocations in the films. These dislocations are shown to behave as “growth dislocations,” which are replicated during growth approximately along the facet normal and so are deflected out from the center of the selective epitaxial regions.

112 citations


"Germanium Based Field-Effect Transi..." refers background in this paper

  • ...[59] developed a model to determine the optimal dimensions, or aspect ratio (AR=height/width), of the trenches....

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Journal ArticleDOI
TL;DR: Germanium metal-insulator-semiconductor capacitors with La2O3 dielectrics deposited at high temperature or subjected to post deposition annealing show good electrical characteristics, especially low density of interface states Dit in the 1011eV−1cm−2 range, which is an indication of good passivating properties.
Abstract: Germanium metal-insulator-semiconductor capacitors with La2O3 dielectrics deposited at high temperature or subjected to post deposition annealing show good electrical characteristics, especially low density of interface states Dit in the 1011eV−1cm−2 range, which is an indication of good passivating properties. However, the κ value is estimated to be only about 9, while there is no evidence for an interfacial layer. This is explained in terms of a spontaneous and strong reaction between La2O3 and Ge substrate to form a low κ and leaky La–Ge–O germanate over the entire film thickness, which, however, raises concerns about gate scalability. Combining a thin (∼1nm) La2O3 layer with thicker HfO2 degrades the electrical characteristics, including Dit, but improves gate leakage and equivalent oxide thickness, indicating a better potential for scaling. Identifying suitable gate dielectric stack which combines good passivating/interfacial properties with good scalability remains a challenge.

109 citations

Trending Questions (1)
What are the challenges and opportunities in the field of Ge optics?

The provided paper does not discuss the challenges and opportunities in the field of Ge optics. The paper focuses on the challenges and opportunities of germanium-based field-effect transistors.