Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
Citations
More filters
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
References
More filters
TL;DR: In this paper, the inversion behaviors of atomic-layer-deposition Al2O3/n-In0.53Ga0.47As capacitors are studied by various surface treatments and postdeposition annealing using different gases.
Abstract: The inversion behaviors of atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors are studied by various surface treatments and postdeposition annealing using different gases. By using the combination of wet sulfide and dry trimethyl aluminum surface treatment along with pure hydrogen annealing, a strong inversion capacitance-voltage (C-V) response is observed, indicating a remarkable reduction in interface trap state density (Dit) at lower half-part of In0.53Ga0.47As band gap. This low Dit was confirmed by the temperature independent C-V stretch-out and horizontal C-V curves. The x-ray photoelectron spectroscopy spectra further confirm the effectiveness of hydrogen annealing on the reduction of native oxides.
108 citations
TL;DR: The deposition behavior of HfO2 by metalorganic chemical vapor deposition on germanium has been investigated in this article, showing that much thinner interfacial layers can be obtained, approximately half the thickness of what is typically found for depositions on silicon, suggesting the possibility of more aggressive oxide thickness∕leakage scaling.
Abstract: The deposition behavior of HfO2 by metalorganic chemical vapor deposition on germanium has been investigated. HfO2 films can be deposited on Ge with equally good quality as compared to high-k growth on silicon. Surface preparation is very important: compared to an HF-last, NH3 pretreatments result in smoother films with strongly reduced diffusion of germanium in the HfO2 film, resulting in a much better electrical performance. We clearly show that much thinner interfacial layers can be obtained, approximately half the thickness of what is typically found for depositions on silicon, suggesting the possibility of more aggressive equivalent oxide thickness∕leakage scaling.
104 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...This is made more difficult by the fact that Ge has a tendency to diffuse into the high-k material [103,140]; although some materials have shown to be more resistant to Ge up-diffusion and can even act as a barrier to it (Al2O3 is an example) [14]....
[...]
...Some works have observed that suppressing Ge interdiffusion with the high-k material results in improved performance [14,140]; suggesting defects are created during the interdiffusion process....
[...]
TL;DR: In this paper, N-type and p-type GaSb metal-oxide-semiconductor capacitors with atomic layer-deposited (ALD) and plasma-enhanced-ALD (PEALD) Al2O3 dielectrics are studied to identify the optimum surface preparation and oxide deposition conditions for a high quality oxide-smiconductor interface.
Abstract: N-type and p-type GaSb metal-oxide-semiconductor capacitors (MOSCAPs) with atomic-layer-deposited (ALD) and plasma-enhanced-ALD (PEALD) Al2O3 dielectrics are studied to identify the optimum surface preparation and oxide deposition conditions for a high quality oxide-semiconductor interface. The ALD Al2O3/GaSb MOSCAPs exhibit strongly pinned C-V characteristics with high interface state density (Dit) whereas the PEALD Al2O3/GaSb MOSCAPs show unpinned C-V characteristics (low Dit). The reduction in Sb2O3 to metallic Sb is suppressed for the PEALD samples due to lower process temperature, identified by x-ray photoelectron spectroscopy analysis. Absence of elemental Sb is attributed to unpinning of Fermi level at the PEALD Al2O3/GaSb interface.
103 citations
TL;DR: In this paper, the InGaSb was grown by molecular beam epitaxy, resulting in a splitting of the heavy and light-hole valence bands and an enhancement of the mobility.
Abstract: Quantum wells of InGaSb clad by AlGaSb were grown by molecular beam epitaxy. The InGaSb is in compressive strain, resulting in a splitting of the heavy- and light-hole valence bands and an enhancement of the mobility. The mobility was found to increase with increasing InSb mole fraction for values of strain up to 2%. Room-temperature mobilities as high as 1500cm2∕Vs were reached for 7.5nm channels of In0.40Ga0.60Sb. These results are an important step toward the goal of high-performance p-channel field-effect transistors for complementary circuits operating at extremely low power.
102 citations
01 Dec 2010
TL;DR: In this article, a Ge p-channel QWFET with scaled TOXE = 14.5A and mobility of 770 cm2/V*s at n s = 5×1012 cm−2 was demonstrated.
Abstract: In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5A and mobility of 770 cm2/V*s at n s =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 A, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.
101 citations
"Germanium Based Field-Effect Transi..." refers background or methods in this paper
...The optimum thickness of this layer appears to be approximately 6–8 ML [10,15]....
[...]
...Co-integration with n-channel InGaAs based MOS-QWFETs, as shown in Figure 15, offers an attractive pathway to extreme-high mobility CMOS....
[...]
...This results in a more scalable device with faster switching, lower dynamic power consumption and minimized Ioff [15]....
[...]
...Figure 11 shows the Ge device research vehicle and compares three different device architectures: (i) conventional MOSFET, (ii) the QWFET, and (iii) metal-oxide quantum well FET (MOS-QWFET)....
[...]
...The hybrid architecture, the MOS-QWFET, shows clear advantages in terms of higher Ion and lower Ioff....
[...]