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Journal ArticleDOI

Germanium Based Field-Effect Transistors: Challenges and Opportunities

19 Mar 2014-Materials (MDPI AG)-Vol. 7, Iss: 3, pp 2301-2339
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

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Citations
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Journal ArticleDOI
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

512 citations

Journal ArticleDOI
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

116 citations

Journal ArticleDOI
17 Jan 2017-ACS Nano
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...

73 citations

Journal ArticleDOI
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.

65 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

49 citations

References
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Journal ArticleDOI
TL;DR: In this article, the atomic layer deposition (ALD) of HfO2 high-κ dielectric layers on HF-cleaned Ge substrates was studied, and the growth per cycle was larger in the first reaction cycles than the steady growth each cycle of 0.04nm.
Abstract: Germanium combined with high-κ dielectrics has recently been put forth by the semiconductor industry as potential replacement for planar silicon transistors, which are unlikely to accommodate the severe scaling requirements for sub-45‐nm generations. Therefore, we have studied the atomic layer deposition (ALD) of HfO2 high-κ dielectric layers on HF-cleaned Ge substrates. In this contribution, we describe the HfO2 growth characteristics, HfO2 bulk properties, and Ge interface. Substrate-enhanced HfO2 growth occurs: the growth per cycle is larger in the first reaction cycles than the steady growth per cycle of 0.04nm. The enhanced growth goes together with island growth, indicating that more than a monolayer coverage of HfO2 is required for a closed film. A closed HfO2 layer is achieved after depositing 4–5HfO2 monolayers, corresponding to about 25 ALD reaction cycles. Cross-sectional transmission electron microscopy images show that HfO2 layers thinner than 3nm are amorphous as deposited, while local epita...

95 citations


"Germanium Based Field-Effect Transi..." refers background in this paper

  • ...deposition (MDB) [80,81], and atomic layer deposition (ALD) (two variations: thermal [82], and plasma [83])....

    [...]

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate that the compound SrHfO3 grown epitaxially on Si(100) by molecular-beam epitaxy is a potential gate dielectric to fabricate n- and p-metaloxide semiconductor field effect transistors with equivalent oxide thickness (EOT) below 1nm.
Abstract: The authors demonstrate that the compound SrHfO3 grown epitaxially on Si(100) by molecular-beam epitaxy is a potential gate dielectric to fabricate n- and p-metal-oxide semiconductor field-effect transistors with equivalent oxide thickness (EOT) below 1nm. The electrical properties on capacitors and transistors show low gate leakage and good capacitance and I-V output characteristics. The lower electron and hole mobilities, which are strongly limited by charge trapping, nevertheless fit well with the general trend of channel mobility reduction with decreasing EOT.

94 citations

Journal ArticleDOI
TL;DR: In this paper, the authors obtained ultrahigh room-temperature (RT) hole Hall and effective mobility in Si0.3Ge0.7 heterostructures with very small parallel conduction.
Abstract: We have obtained ultrahigh room-temperature (RT) hole Hall and effective mobility in Si0.3Ge0.7/Ge/Si0.3Ge0.7 heterostructures with very small parallel conduction. Reducing parallel conduction was achieved by employing Sb doping in Si0.3Ge0.7 buffer layers, which drastically increased RT hole Hall mobility up to 2100 cm2/V s in the strained Ge channel modulation-doped structures and improved device characteristics of the p-type metal–oxide–semiconductor field-effect transistors with the strained Ge channel. The peak effective mobility reached to 2700 cm2/V s at RT, which was much higher than the bulk Ge drift mobility.

94 citations

Journal ArticleDOI
TL;DR: In this paper, the gate current conduction mechanism through the GeO2/Ge metaloxide-semiconductor structure is dominated by Fowler-Nordheim tunneling, and the barrier height between Ge and GeO 2 is evaluated to be 1.2-1.4 eV.
Abstract: We have fabricated GeO2/Ge interfaces on (100), (110), and (111) orientation substrates by direct thermal oxidation. The x-ray photoelectron spectroscopy analyses suggest that the Ge oxides are composed of GeO2 and have almost the same interfacial structure, independent of the surface orientations. The gate current conduction mechanism through the GeO2/Ge metal-oxide-semiconductor structure is dominated by Fowler–Nordheim tunneling. In addition, the barrier height between Ge and GeO2 is evaluated to be 1.2–1.4 eV. In interface trap density (Dit) measurement by using the low temperature conductance method, the amount of Dit in the conduction band side is also almost the same, while Dit in the valence band side is lowest for the (111) surface. Minimum detectable Dit is lower than 1×1011 eV−1 cm2 for all the orientations. These surface orientation dependences of the GeO2/Ge interface properties are quite different from those of the SiO2/Si interface.

94 citations

Journal ArticleDOI
TL;DR: In this article, the effective masses for relaxed and biaxially strained Si, Ge, III-V compound semiconductors and their alloys on different interface orientations were calculated using nonlocal empirical pseudopotential with spin-orbit interaction.
Abstract: Electronic band structure and effective masses for relaxed and biaxially strained Si, Ge, III–V compound semiconductors (GaAs, GaSb, InAs, InSb, InP) and their alloys (InxGa1−xAs, InxGa1−xSb) on different interface orientations, (001), (110), and (111), are calculated using nonlocal empirical pseudopotential with spin-orbit interaction. Local and nonlocal pseudopotential parameters are obtained by fitting transport-relevant quantities, such as band gap and deformation potentials, to available experimental data. A cubic-spline interpolation is used to extend local form factors to arbitrary q and to obtain correct workfunctions. The nonlocal and spin-orbit terms are linearly interpolated between anions and cations for III–V semiconductors. The virtual crystal approximation is employed for the InxGa1−xAs and InxGa1−xSb alloys and deformation potentials are determined using linear deformation-potential theory. Band gap bowing parameters are extracted using least-square fitting for relaxed alloys and for strai...

94 citations

Trending Questions (1)
What are the challenges and opportunities in the field of Ge optics?

The provided paper does not discuss the challenges and opportunities in the field of Ge optics. The paper focuses on the challenges and opportunities of germanium-based field-effect transistors.