Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
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01 Dec 2010
TL;DR: In this paper, the authors systematically investigated Ge interface passivation methods, and the highest electron and hole mobility have been demonstrated by dramatic reduction of D it through the collaboration of self-passivation and valency passivation.
Abstract: We have systematically investigated Ge interface passivation methods, and the highest electron (1920 cm2/Vs) and hole mobility (725 cm2/Vs) have been demonstrated by dramatic reduction of D it through the collaboration of self-passivation and valency passivation. In Si passivation, it is found that Si contributes to the upper half (worse) and lower one (better) in the bandgap differently. This study strongly suggests us that high performance Ge CMOS is really feasible.
84 citations
TL;DR: In this paper, the inversion capacitance increases with air exposure time for Au/GeO2/Ge MOS capacitors, while maintaining an interface state density (Dit) of about a few 1011 cm−2'eV−1.
Abstract: Improvement in electrical properties of thermally grown GeO2/Ge metal-oxide-semiconductor (MOS) capacitors, such as significantly reduced flatband voltage (VFB) shift, small hysteresis, and minimized minority carrier response in capacitance-voltage (C-V) characteristics, has been demonstrated by in situ low temperature vacuum annealing prior to gate electrode deposition. Thermal desorption analysis has revealed that not only water but also hydrocarbons are easily infiltrated into GeO2 layers during air exposure and desorbed at around 300 °C, indicating that organic molecules within GeO2/Ge MOS structures are possible origins of electrical defects. The inversion capacitance, indicative of minority carrier generation, increases with air exposure time for Au/GeO2/Ge MOS capacitors, while maintaining an interface state density (Dit) of about a few 1011 cm−2 eV−1. Unusual increase in inversion capacitance was found to be suppressed by Al2O3 capping (Au/Al2O3/GeO2/Ge structures). This suggests that electrical d...
81 citations
TL;DR: In this paper, a slot-plane-antenna (SPA) high density radical oxidation was used to grow a metal-oxide-semiconductor (Al2O3) gate stack with a GeO2 interfacial layer.
Abstract: GeO2 was grown by a slot-plane-antenna (SPA) high density radical oxidation, and the oxidation kinetics of radical oxidation GeO2 was examined. By the SPA radical oxidation, no substrate orientation dependence of growth rate attributed to highly reactive oxygen radicals with low oxidation activation energy was demonstrated, which is highly beneficial to three-dimensional structure devices, such as multigate field-effect transistors, to form conformal gate dielectrics. The electrical properties of an aluminum oxide (Al2O3) metal-oxide-semiconductor gate stack with a GeO2 interfacial layer were investigated, showing very low interface state density (Dit), 1.4×1011 cm−2 eV−1. By synchrotron radiation photoemission spectroscopy, the conduction and the valence band offsets of GeO2 with respect to Ge were estimated to be 1.2±0.3 and 3.6±0.1 eV, which are sufficiently high to suppress gate leakage.
80 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...Recently, researchers have shown some success in improving interface quality by capping the GeO2/Ge interface with diffusion resistant high-k material [13,14,138]....
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...A wide variety of oxidation methods are being explored, including thermal oxidation [12,71,102,119–130], ozone or atomic oxygen exposure [131–136], high-pressure oxidation [103,104,137], radical oxidation [138], and plasma techniques [9,14,139]....
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TL;DR: In this paper, a method based upon molecular beam epitaxy and solid-phase epitaxy is described to make two-dimensional, single crystal films of silicon or germanium on top of this oxide.
Abstract: Future microelectronics will be based upon silicon or germanium-on-insulator technologies and will require an ultrathin (<10 nm), flat silicon or germanium device layer to reside upon an insulating oxide grown on a silicon wafer. The most convenient means of accomplishing this is by epitaxially growing the entire structure on a silicon substrate. This requires a high quality crystalline oxide and the ability to epitaxially grow two dimensional, single crystal films of silicon or germanium on top of this oxide. We describe a method based upon molecular beam epitaxy and solid-phase epitaxy to make such structures and demonstrate working field-effect transistors on germanium-on-insulator layers.
79 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...[64] obtained a single-crystalline fully-relaxed layer (4 nm) of Ge on a (LaxY1–x)2O3/Si(111) template....
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01 Oct 2010
78 citations
"Germanium Based Field-Effect Transi..." refers background or methods in this paper
...The ART approach has been shown to produce narrow regions of excellent quality Ge, and has already been used in a commercial product [61]....
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...For some device applications long 20 μm wide patches of high quality Ge may be sufficient [61]....
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