Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
References
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01 Jan 2010
TL;DR: The use of germanium and III-V compounds as potential replacements for silicon channels has attracted lots of attention for its application in advanced pMOS devices as discussed by the authors, and Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS device beyond 14 nm node technology.
Abstract: Over the last years there has been lots of interest in the use of germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility has attracted lots of attention for its application in advanced pMOS devices. Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS devices beyond 14 nm node technology.
54 citations
TL;DR: In this paper, the authors developed an alternative deposition process at 350°C using Si 3 H 8 which significantly decreases the Ge peak at the Si surface and attributed this strong reduction mainly to the fact that growth at 350-°C from trisilane proceeds below the Si-H desorption temperature.
53 citations
01 Dec 2007
TL;DR: In this paper, the peak hole mobility of PtGe source/drain p-MOSFETs is achieved by inserting ultra-thin GeOx layer between metal and Ge, which enables them to operate metal source/draining Ge n-mOSFets for the first time.
Abstract: GeO2/Ge and high-k(LaYO3)/Ge interfaces have been significantly improved by suppressing GeO desorption and treating Ge surface with radical nitrogen. With the Ge- intimate material selection and interface conscious process flow, we have achieved that the peak hole mobility of PtGe source/drain p-MOSFET is about 370 cm2/Vsec in FUSI/GeO2/Ge. Furthermore, metal/n-Ge ohmic characteristic has been achieved by inserting ultra-thin GeOx layer between metal and Ge, which enables us to operate metal source/drain Ge n-MOSFETs for the first time.
48 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...However, for the GeOx/Ge interface, even 10 11 cm −2 ·eV −1 is very difficult to achieve [117,118]....
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...By comparison to the SiO2/Si interface, the GeOx/Ge interface is far less thermodynamically stable....
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...Zhang et al. [14] demonstrated an EOT of about 1 nm and midgap Dit on the order of 1 × 10 11 cm −2 ·eV −1 using a Al2O3/GeOx/Ge gate stack....
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...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....
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...The approach of capping the GeOx with a layer of diffusion-resistant high-k material is an excellent step in achieving this....
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TL;DR: In this paper, an ultrathin MgO layer between CoFeB and Ge was demonstrated to significantly reduce the Schottky barrier height and contact resistances of spin diodes.
Abstract: We demonstrated that an ultrathin MgO layer between CoFeB and Ge modulated the Schottky barrier heights and contact resistances of spin diodes. We confirmed that, surprisingly, an insulating MgO layer significantly decreased the Schottky barrier heights and contact resistances of spin diodes on N+Ge, opposite to the increase observed for P+Ge. A 0.5 nm thick MgO layer on N+Ge decreases the Schottky barrier height from 0.47 to 0.05 eV and lowers the minimum contact resistance 100-fold to 1.5×10−6 Ω m2. These results open a pathway for high efficient spin injection from ferromagnetic materials and semiconductors.
48 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....
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TL;DR: In this article, an Al2O3/GeO2 gate-dielectric stack was fabricated on p-type Ge by electron cyclotron-resonance plasma oxidation and sputtering without external substrate heating.
Abstract: We have fabricated an Al2O3/GeO2 gate-dielectric stack on p-type Ge by electron-cyclotron-resonance plasma oxidation and sputtering without external substrate heating. We show that the midgap interface state density at the GeO2/Ge interface is 4.5 × 1010 cm-2 · eV-1. The hysteresis observed in capacitance-voltage measurements is reduced to 50 mV when the gate bias is swept from accumulation to inversion and back to accumulation or after a single dummy sweep from inversion to accumulation, indicating the possibility that the bulk oxide traps causing the hysteresis are deactivated by the injected holes. The band gap of GeO2 was determined by internal photoemission measurements to be 4.7 eV. The conduction- and valence-band offsets at the GeO2/Ge interface are moderately symmetric and large with values of 1.8 and 2.2 eV, respectively. These promising results suggest that low-temperature plasma-grown GeO2 is a suitable interlayer between high-dielectric-constant dielectrics and Ge.
47 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...A wide variety of oxidation methods are being explored, including thermal oxidation [12,71,102,119–130], ozone or atomic oxygen exposure [131–136], high-pressure oxidation [103,104,137], radical oxidation [138], and plasma techniques [9,14,139]....
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